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Maximizing the battery life time of mobile devices and sensor nodes increasingly becomes a challenge, and receiver power consumption tends to become more problematic than delivering adequate transmit power. We address the challenge of achieving the highest possible throughput per Watt of receiver circuit power. Our results show that optimum and adaptive tuning of the front-end parameters of the receiver...
This work presents an integrated ultra high frequency (UHF), broadband direct-conversion receiver. The receiver integrates a single-ended RFVGA, an on-chip single-to-differential balun, a current-mode passive mixer, and a combination of continuous and discrete-time baseband filter with built-in anti-aliasing. Targeted to operate between 470-862 MHz, the receiver achieves a noise figure of 7.9dB, an...
This article presents a UWB receiver, which is made by the chips designed by our group in SMIC0.18 um process, This receiver was verified by the measurement, With the help of FPGA it can synthesis 2.8G~3.98 GHz LO frequency by changing the PLL and reference frequency, with reference frequency 21 MHz, division ratio 1/160, it can be locked at 3.36 GHz with the phase noise of -83 dBc/Hz, the internal...
This paper presents a channelized jamming reconnaissance receiver, and analyzed false response, amplitude response and temperature drift, which influence the performance of channelized receiver. For the sake of interchangeableness, we divided the receiver into RF assembly and IF assembly, then compensated each assembly independently and estimated system error. At last, we tested the receiver under...
A multiple-input-multiple-output (MIMO) receiver with reduced complexity has been introduced. The receiver selects the outputs of L antennas from N available antennas. Then; a single time-multiplexed RF front end down converts the signals of L antennas to the baseband. This implies that only one RF front-end may be used. It is shown by use of the analytical and simulation studies that a full diversity...
This paper summarizes the development of safety-of-life receivers for global navigation satellite systems (GNSS) that has been being conducted at the Institute of Communications and Navigation of the German Aerospace Center (DLR). Two receiver systems have already been successfully fabricated, integrated and tested by means of field experiments. Implementation issues of these two systems are described...
This contribution deals with the complete design of a multi-standard GPS/GALILEO front-end, from setting the specifications through to the complete characterization of the device. Special focus will be given to the design for test and the characterization of the design, as optimizing the time spent on this improves time-to-market for the product under development. The highly integrated, low power...
Building compact and low-cost yet flexible and reconfigurable radios for future wireless systems is generally a challenging task. On one hand, the needs for flexibility and re-configurability prevent using dedicated hardware particularly designed and optimized for only a single application or part of the radio spectrum. And on the other hand, to keep the overall size and cost of the radio equipment...
We describe a novel wireless receiver architecture that is a broadband generalization of narrowband heterodyning systems commonly used in radio. It can be constructed with cochlea-like traveling-wave structures. We show how this architecture exploits the efficiency of cochlear spectrum analysis to perform parallel, multi-scale analysis of wideband signals. We discuss analogies between spectrum analysis...
A 2.4 GHz reference-less single chip wireless receiver for 1 Mbps QPSK demodulation is presented. The receiver accomplishes LO carrier recovery and data demodulation directly from the received RF signal without resort to resonator based reference, such as crystal oscillator. Integrating LNA, mixer, LO carrier recovery loop, post amplifier, and digital demodulator on a single chip, the total power...
A direct conversion receiver is demonstrated which operates in the presence of a rail-to-rail (+12.4dBm) out-of-band blocker and a -16.3dBm blocker, where the ICP1 is +12.5dBm and the uncorrected extrapolated IIP3 is +33.5dBm. IM distortion is adaptively cancelled via feedforward loops which are digitally expanded to reproduce higher order nonlinear reference terms. Cancellation improves input-referred...
A pHEMT broadband image rejection receiver with an image rejection ratio (IRR) more than 20 dB from 54 GHz to 66 GHz is presented using varactor tuning topology. Tunable varactors connected in shunt between an RF coupler and mixers are used to control the phase and amplitude of two RF signals. It offers the IRR improvement of 3.1~21.4 dB in the cost of gain degradation below 1.1 dB from 54 GHz to...
We have developed a low-power, fully integrated receiver for 24-GHz ISM band wireless communication using a Rich-Transformer Direct-Stacked/Coupled (RT-DSC) technique. This technique makes it possible to reduce supply voltage and current without any performance degradation. The 24-GHz receiver circuit was fabricated using 0.18-μm SiGe BiCMOS technology. Receiver gain of 30 dB and noise figure (NF)...
In this work a highly integrated, ultra-low-power BPSK receiver for short-range wireless communications is presented. The receiver consists of a power divider, two injection-locked RC oscillators with limiting buffers and an XOR output stage. The demodulation principle is based on the dynamic phase response of the two BPSK signal injected oscillators. As proof of concept, a 300 MHz receiver was implemented...
This paper presents a digital-intensive RF sampling receiver composed of a noise-canceling bandpass low-noise amplifier (LNA) and an RF analog-to-digital converter (ADC) for multi-band multi-mode wireless communication. The proposed LNA employs an on-chip transformer to combine the outputs of a common-gate and a common-source LNA to reduce the noise figure and enhance the linearity, while providing...
A dual-band RF receiver front-end for DVB-H is presented in this paper. It includes two sets of single-ended input LNAs, respectively followed by a double-balanced current-driven passive mixer with a low impedance load. The receiver front-end is implemented in a 1P6M 65 nm CMOS process and occupies a total chip area of 2.17 mm2. It exhibits a conversion gain of 36.5 dB, an IIP3 of -13.1 dBm, an IIP2...
This contribution deals with the novel conception of design approach to RF wideband and multiband receivers. New methodology of spatial sampling and spatial sampling method of standing wave is presented. Front-end RFIC receiver, utilizing spatial sampling method of standing wave for down converting to baseband and demodulation, has been proposed and analyzed. The whole system is proposed to be implemented...
This paper presents a new method for testing radio frequency (RF) receivers that utilizes a multitone digital signal generation scheme and relies on the analysis of the receiver baseband output to compute the RF performance parameters. The proposed method takes out the cost of expensive RF instrumentation on the input side of receiver testing and only requires the less expensive baseband digitization...
This paper deals with the design and analysis of a new RF subsampling downconversion front-end assigned to propose a multistandard receivers for next wireless generation standards. The RF subsampling front-end is based on continuous time (CT) bandpass ΣΔ modulator with sine-shaped feedback DAC. Much attention is given to frequency sampling selection and non idealities in subsampling CT-bandpass ΣΔ...
In contemporary communication satellite systems, a digital processing unit on board the satellite can be employed to filter, channelize, and switch the uplink communication signals. This processing is performed subsequent to the radio frequency (RF) to intermediate frequency (IF) downconversion of the uplinked signals. Then, an analog-to-digital converter (ADC) is employed to convert the analog signals...
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