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A stacked amplifier architecture has been used to achieve high RF output power levels in sub-100nm CMOS. The stacking makes it possible to both operate the power amplifier (PA) from a large supply voltage and implement RF power combining. As a proof of concept, a 6.5-GHz PA has been integrated in a 65-nm standard CMOS technology. The amplifier achieves 27.4-dBm output power with an efficiency of 19...
We present a novel fully differential input/output distributed transformer topology used for the design of millimeter-wave power amplifiers. Input/output distributed transformers are used to feed the input signal to four differential couples and to combine their output power. This topology improves the stability and the efficiency of the power amplifier, minimizing the chip area. The PA prototype...
A 3-5GHz CMOS low noise amplifier (LNA) for ultra wide band (UWB) receiver based on CMOS 0.18μm process is presented in this paper. To achieve low-power consumption and low noise, the proposed LNA employs current-reused technique via a PMOS cascade stage. The LNA provides a maximum forward gain (S21) of 11dB while drawing 6mW from 1.2-V supply voltage. The LNA achieves 2.6-3.9dB noise figure (NF)...
This paper presents a response-translation technique to realize an ultra-low-cutoff lowpass filter in small area for biopotential acquisition systems. It is by exploiting a chopper-stabilized instrumentation amplifier (IA) with bandpass characteristic to obtain a lowpass response after chopper stabilization, resulting in substantial area savings because of relaxed time constant in the implementation...
A 25 Gb/s × 4-channel transimpedance amplifier has been realized in 65-nm CMOS technology. It achieves transimpedance gain of 69.8 dBΩ, bandwidth of 22.8 GHz, and gains flatness of under ±2 dB after equalizing the effect of transmission loss, incorporating gain-stage amplifier with flat frequency response, and 50Ω-output driver with an analogue equalizer. The proposed TIA dissipates only 74 mW/ch...
A low-power, 40-Gb/s optical transceiver front-end is demonstrated in a 45 nm silicon on insulator (SOI) CMOS technology. A modulator driver uses floating body devices to realize voltage swing of 2 VPP with a small-signal gain of 7.6 dB over 33 GHz. The optical receiver consists of a transimpedance amplifier (TIA) and post-amplifier with 55-dB·Ω of transimpedance over 30 GHz. The group-delay variation...
A CMOS heterodyne receiver integrating a phase-locked loop that includes a bulk of transmitter functions for W-band pulsed radar is realized using low leakage transistors of a low cost 65-nm bulk CMOS process with 5 thin and 1 thick metal layers used to manufacture cell phone RFIC's. The peak conversion gain of receiver is 7 dB and the minimum NF is 10.8 dB between 78 and 88 GHz in measurement. The...
This study was initiated to design a low noise amplifier (LNA), which could work with ultra low voltage of 0.5V and was optimized for WSN application using SMIC 0.13 μm RF-CMOS technology. The topology of differential inductance degenerated folded cascode based on power-constrained simultaneous noise and input matching (PCSNIM) technique was adopted. Chosen circuit demonstrated a power gain of 16...
A fully integrated double frequency differential LC voltage controlled oscillator (VCO), used in the frequency synthesizer of 2.4GHz IEEE802.15.4/ZigBee Wireless Sensor Network (WSN), is designed and implemented based on TSMC 0.18μm RF CMOS process with low power dissipation and wide tuning range. The core circuit adopts complementary differential negative resistance LC oscillator structure and is...
A fully integrated double frequency differential LC voltage controlled oscillator (VCO), used in the frequency synthesizer of 2.4GHz IEEE802.15.4/ZigBee Wireless Sensor Network (WSN), is designed and implemented based on TSMC 0.18 μm RF CMOS process with low power dissipation and wide tuning range. The core circuit adopts complementary differential negative resistance LC oscillator structure and is...
This paper proposes a CMOS 6 bit A/D converter with input voltage range detectors based upon folding amplifier with a folded-cascode load. The input voltage range detectors allow the proposed A/D converter to reduce the power dissipation by turning on one fourth of all the comparators. The measurement result illustrates ENOB of 5.1 bits at 250Msps, power dissipation of 106mW, and FoM of 17.5pJ/steps.
In this paper, the design, implementation and simulation of a high-transimpedance gain, ultra low-power dissipation and low-noise CMOS front-end transimpedance amplifier (TIA) is presented. For interfacing with bio-sensor array and analog neuron circuit, an improved capacitive-feedback TIA topology is adopted with active load to obtain a 131 M gain, 1.45 MHz bandwidth, 90.8fA/rt(Hz) input-referred...
A K-band low-noise amplifier (LNA) is designed and fabricated in a standard 0.18 μm CMOS technology. A design method of CMOS LNA is used to render the optimum source resistance (Ropt) close to 50 Ω and Zin=Zopt* by using small devices and small bias currents. This LNA chip achieves a peak gain of 13.5 dB and a noise figure of 4.7 dB at 24 GHz. The supply voltage and current are 1 V and 8.3 mA, respectively...
For applications requiring low-power low-voltage and real-time, a novel analog VLSI implementation of continuous Marr wavelet transform based on CMOS log-domain integrator is proposed. Marr mother wavelet is approximated by a parameterized class of function. By using a hybrid particle swarm optimization algorithm (PSO) combined with the sequential quadratic programming (SQP), the optimum parameters...
A new combined AC/DC-coupled output averaging technique for input amplifier design of flash analog-to-digital converters (ADC) is presented. The new offset averaging design technique takes full advantages of traditional DC-coupled resistance averaging and AC-coupled capacitance averaging techniques to minimize offset-induced ADC nonlinearities. Circuit analysis allows selection of optimum resistance...
The paper presented a 2.4GHz fully integrated CMOS power amplifier using capacitive cross-coupling, fabricated in 0.18μm CMOS. With a 3.3-V supply voltage, PAEmax and PAE at 1 dB compression point are 34.3% and 26.8%. P1dB, Psat, and PG are 25.2dBm, 27.7dBm and 26.5dB, respectively. The advantages of the proposed capacitive-cross-coupled PA are the improvement of reverse isolation and the area saving.
A kind of novel CMOS optically coupled isolation amplifier (OCIA) composed of two operational amplifiers (OAs) is present. To improve the linearity and reduce the power consumption, the negative feedback signal is introduced to the input loop through two photoelectric coupled devices. Besides, other improvement actions are taken in this amplifier. Experimental results show that compared with the BiCMOS...
As CMOS technology continues to evolve, the supply voltages are decreasing while at the same time the transistor threshold voltages are remaining relatively constant. Making matters worse, the inherent gain available from the nano-CMOS transistors is dropping. Traditional techniques for achieving high-gain by cascoding become less useful in nano-scale CMOS processes. Horizontal cascading (multi-stage)...
This paper presents a low power, high gain, fully differential ultra-wide bandwidth operational amplifier with wide dynamic range. The design uses two-stage gain, high swing common-mode feedback, `doublet-free' pole-zero cancellation and gm-boosting techniques to increase the unity gain frequency to about 1.5 times that of the widely used class-A common source output stage at similar power consumption...
A micropower high-gain, low-noise differential difference amplifier (DDA) is presented in this paper. The new circuit incorporates the gate-bulk driven transistor pairs for input stage transconductance enhancement; the very high gain folded telescopic cascode structure that permits small headroom operation; and the replica tracking bias that sustains the circuit performance against variations of process,...
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