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The SRAM cells that form the configuration memory of an SRAM-based FPGA make such FPGAs particularly vulnerable to soft errors. A soft error occurs when ionizing radiation corrupts the data stored in a circuit. The error persists until new data is written. Soft errors have long been recognized as a potential problem as radiation can come from a variety of sources. This paper presents an FPGA fault...
In this paper, the Test Pattern Generation (TPG) with a new simple hybrid (dynamic and static) compaction technique for combinational logic circuits and systems is presented. Digital systems are implemented nowadays on an advance VLSI technology, which is called Field Programmable Gate Array (FPGA). The test procedure requires a deliberate introduction of faults in the System Under Test (SUT). FPGA...
This paper presents a silicon-proven fault tolerant FPGA architecture that can repair a wide range of hardware faults. This new architecture does not require fine-grained location of fault, and the error map is stored in non-volatile memory that is monolithically integrated on top of the CMOS circuit. Redundancy operations are fully self-contained and do not affect data streaming in and out of the...
SRAM-Based FPGAs are widely employed in space and avionics computing. The unfriendly environment and FPGA radiation sensibility can have dramatic drawbacks on the application reliability. The partial self-reconfiguration ability gives an excellent aid to counteract single event upsets (SEUs) caused by excessive silicon ionization, and the consequent system misbehavior. Related to this feature, fault...
Over the last decade, several Fault-Tolerant techniques for FPGAs were proposed especially for recovering from permanent faults. Most of those techniques were based on relocation of the defective module into a new location acting as a spare. Accordingly, what is the suitable number of spares that should be added to a system? In this paper, a performability model is developed to quantitatively investigate...
Various optimized coordinate rotation digital computer (CORDIC) designs have been proposed to date. Nonetheless, in the presence of natural faults, such architectures could lead to erroneous outputs. In this paper, we propose error detection schemes for CORDIC architectures used vastly in applications such as complex number multiplication, and singular value decomposition for signal and image processing...
This article presents the development of an experimental system to introduce faults in Trivium stream ciphers implemented on FPGA. The developed system has made possible to analyze the vulnerability of these implementations against fault attacks. The developed system consists of a mechanism that injects small pulses in the clock signal, and elements that analyze if a fault has been introduced, the...
Single Event Upsets (SEUs) inadvertently change the logic memory and thereby the configuration of the Field Programmable Gate Arrays (FPGAs), leading to their incorrect functioning. Traditional methods to tolerate such faults include Triple Modular Redundancy (TMR). However, such method has a high overhead in terms of power and area. Moreover, the inexact methods used in ASICs to overcome this problem...
This paper proposes a hierarchical fault injection emulation framework tailored to the structure of complex and large application-specific circuits, that performs vulnerability analysis of the system for single event upsets (SEUs) at different design granularities in real-time. In particular, the framework allows for efficient probabilistic modelling of the SEU impact, making it particularly applicable...
This paper proposes a method for improvement of the fault-coverage capabilities of Field Programmable Gate Array (FPGA) designs. It utilizes Concurrent Error Detection (CED) techniques and the basic architectures of actual modern FPGAs the Look-Up Table (LUT) with two outputs. Proposed Parity Waterfall method is based on a cascade (waterfall) of several waves of inner parity generating the final parity...
Soft processors in SRAM-based FPGAs are gaining acceptance as enabling technology for building embedded systems in several market domains, even for critical applications such as space, transportation and medical devices. However, due to the high vulnerability of SRAM-based FPGAs to single-event upsets (SEUs), which is expected to be aggravated in the future, as FPGA devices are moving aggressively...
FPGA is devices that contains large resources of logic gates and RAM blocks to implement complex functions. Reconfigurable hardware based image processing is proposed in this paper. In this work, a novel method of reconfigurable circuit switching is done. An approach to automatic reconstruct of image is presented. An image processing application is chosen to demonstrate the reconfiguration action...
Field Programmable Gate Arrays (FPGAs) are successful platforms for the implementation of communication systems, due to their potential high throughput and low development costs. In such systems, however, investigating the system's resilience to soft errors is crucial in many scenarios, such as when facing stringent dependability constraints or when operating in radiation-harsh environments. Therefore,...
FPGA based embedded system for continuous online monitoring has gained importance in recent years. The existing FPGA based methodologies rely on transient analysis, which unnecessarily gives undue stress to the motor. Also, FFT is used which consumes large resource in the hardware unit. In this paper a DWT based algorithm is designed and implemented in FPGA to detect Broken rotor bar fault using vibration...
Following the decision to choose Rijndael as the successor of Data Encryption Standard (DES), Advanced Encryption Standard (AES) was increasingly used in numerous applications which require confidentiality and the secure exchange of the data. While security is a property increasingly sought for many applications (credit cards, telecommunications …), it becomes necessary to consider physical attacks...
Induction motor plays a key role in ensuring functional execution and smooth progression of modern industries. But due to several harsh operational environments, different types of faults, in the form of stator winding fault, rotor fault etc. develop in the motor. If these faults, which are mostly minor in nature initially, don't get detected in earlier stages then they may inflict major damage in...
Soft-error detection in FPGAs typically requires replication, doubling the required area. We propose an approach which distinguishes between tolerable errors in data-flow, such-as arithmetic, and intolerable errors in control-flow, such as branches and their data-dependencies. This approach is demonstrated in a new high-level synthesis compiler pass called StitchUp, which precisely identifies the...
The differential relay is able to meet its ultimate goal reliably, if it has the characteristics of a simple differential relay during the internal fault condition and percentage differential relay characteristics during external fault. It has been the focus of study to incorporate both these characteristics in a single relay and hence to improve the sensitivity and security of the relay. However,...
Cryptographic implementations are subject to physical attacks. Private circuits II is a proven protection against a strong attacker, able to read and write on a finite number of chosen internal nodes. In practice, side-channel analyses and fault injections are less accurate: typically, classical injection techniques (clock and power glitches, electromagnetic pulses, etc.) can be reproducible, but...
Due to the technology scaling, the reconfigurable SoCs built on SRAM-based FPGAs become more susceptible to radiation and aging effects. This paper proposes an adaptive cross-layer fault recovery solution based on hardware/software co-design for reconfigurable SoCs. By pyramidal structure design and cross-layer adaptivity, our solution gives both consideration to hardware circuit integrity at the...
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