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The thesis designed an SOPC system with network interface. With the basis that LWIP was ported onto the SOPC system, a file format was developed for directly reconstructing the system. The hardware and software system of the SOPC system was upgraded and refreshed through TCP/IP. The thesis implemented the online reconstructable SOPC system based on TCP/IP.
Ethernet based network protocol replaces fieldbus systems due to its high speed, safety, and extendibility. At the system level, use of an additional network requires effort to implement the new environment. The user has to analyze and organize two networks. This paper proposes FPGA based network controller between Ethernet and EtherCAT. It does not incur additional cost and effort. As it is based...
This paper describes an implementation in hardware of Internet Protocol version 4. Routing and addressing features were integrated with Network Interfaces and synthesized to a Stratix II FPGA device. Our work showed two implementations of a full duplex Internet Protocol version 4. The first implementation consists in a Reference design and the second uses the same design but with more buffer space...
This paper presents a proposal of a Gigabit UDP/IP network stack in FPGA, which is the stack of the widely used in VoIP and Video-conference applications. This network node implements the Network, Transport and Link Layer of a traditional stack. This architecture is integrated and developed using Xilinx ISE tool and synthesized to a Spartan-3E FPGA. We show architecture details, timing and area results...
Due to their versatile and generic structure, field programmable gate arrays (FPGA) allow dynamic reconfiguration of their logical resources just by loading configuration files. However, this flexibility also opens up the threat of theft of intellectual property (IP) since these configuration files can be easily extracted and cloned. In this context, the ability to bind a configuration to a specific...
This paper describes implementation of Web server using Altera Nios II embedded IP core, a configurable general purpose embedded RISC processor with embedded peripheral architecture. A Web server is a computer that delivers Web pages to other computers in the network. Every Web server has a unique IP address and possibly a domain name. Any computer can work as Web server by installing server software...
Universal bus interface is very helpful for improving the popularity of the device or equipment on both SoC integration and board level computing system design. Because of the diversity of bus interface accessing protocol, universality is usually unable to be achieved in a common interface design. Through introducing the concept of sequence configuration, a method of designing universal bus interface...
Wireless sensor network has been widely used and its real-time data processing capability is very limited. This paper puts forward a new solution, which is the novel wireless sensor network node design with hyperchaos encryption based on FPGA. With the wide application on wireless sensor network based on ZigBee protocol, we encrypt the transported data in the network using hyperchaos by FPGA, which...
This paper describes the design of a virtualized application and networking infrastructure (VANI) node that can be used to facilitate network architecture experimentation. Currently the VANI nodes provide four classes of physical resources: processing, reconfigurable hardware, storage and interconnection fabric, but the set of sharable resources can be expanded. Virtualization software allows slices...
The dynamic reconfiguration technique based on FPGA (field-programmable gate array) can improve the resource utilization. The dynamic reconfiguration principles and methods are discussed. A remote dynamic reconfiguration scheme using Xilinx Virtex-II FPGA and SMCS Ethernet PHY (physical layer transceiver) is proposed. The hardware of system is designed with Xilinx Virtex-IIXC2V30P FPGA that embeds...
The development of a new tri-modality preclinical Computed Tomography apparatus (??CT), Single Photon Emission Computed Tomography apparatus (??SPECT) and Positron Emission Tomography apparatus (??PET) dedicated to small animal imaging tomography is underway in the group ImaBIO at the Institut Pluridisciplinaire Hubert Curien. The ??CT and ??SPECT scanners are working quite fine and now used by biologists...
This paper presented fieldbus SOPC-based FSB (fast serial bus) controller using FPGA technology for CNC application, which used H/S(hardware/software) codesign method. This controller completed control of AL (application layer), DLL(data link layer) and PL(physical layer). In the controller, CAN-compatible hardware designed by VHDL handled with DLL and PL of FSB, while software run in soft processor...
This paper presents the ANR project IDROMel, which aims at developing reconfigurable SDR (software defined radio) and cognitive radio (CR) equipments. IDROMel is a 3 years project that started in 2005 and finishes in 2009. The main objective of IDROMel is to define, develop and validate a powerful SDR and CR platform combining very last technology progresses. The platform includes software parts (reconfigurable...
PCI Express is rapidly establishing itself as the successor to PCI, which provides higher performance, increased flexibility, and scalability for next-generation systems. FPGA offers a flexible solution for PCI Express compared with ASIC. Using IP Core and designing a DMA module in FPGA, this paper implemented a high-performance PCI Express system. IP Core handles the protocols defined by PCI Express...
EDA vendors have proposed a standard for the sharing of IP among vendors to be used in the design and development of IP for FPGAs. Although, we do not propose any attacks, we show that there are easy ways in which the security of the whole process can be enhanced by using standard cryptographic techniques such as secret sharing and public key based key exchange. We also explore the advantages that...
Web service is a common Internet application that enables interactions of machines over a network. As to establish ubiquitous Internet, enabling Web services on embedded systems is certainly among the development trend in near future. This paper presents an implementation of REST style or RESTful Web services on embedded system. The prototype had been implemented using a Xilinx Spartan-3E Starter...
In this paper we describe a methodology to do rapid hardware prototyping of a part of a digital signal processing system described in Simulink. It explains the main technical problems when trying to go to hardware from a pure functional description and the solutions proposed to solve them. The methodology is applied on a proven model, from the architecture co-simulation, to the real hardware implementation...
Reuse of intellectual property (IP) of VLSI physical design facilitates integration of more components on a single chip in shrinking time-to-market. For intellectual property protection (IPP), various kinds of IP marks are embedded into the design for establishing the veracity of a legal owner. However, public verification of IP marks is not leakage-proof. Current techniques include a sufficiently...
A hardware structure of LXI bus instruments based on Nios II core is presented in this paper. By the translation of muC/OS II operating system and the lwIP stack on the Nios II core, the TCP and IP protocols are realized. The Web server and the Ethernet protocols are also realized by the programming interface supplied by the lwIP stack. Finally the paper tests the network protocols on the LXI module...
Providing flexible satellite communications through frequency- and waveform-agile onboard processing is an emerging trend for missions such as the Air Force's Operationally Responsive Space (ORS). Data packet routing features that seek to improve network flexibility and performance by going beyond traditional ldquobent piperdquo platforms are being leveraged to meet the objectives of ORS. The Programmable...
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