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This paper describes a design of network remote control based on Ethernet controller RTL8019AS and FPGA chip EP3C25Q240C8N. It's through the Altera NIOS II soft-core processor and a simplified TCP/IP protocol LWIP to complete the Ethernet Communication Protocol, and FPGA can configure and control RTL8019AS. Then the information can be communication between FPGA and PC, in order to achieve network...
The configuration data sequence of a Field Programmable Gate Array (FPGA) is an Intellectual Property (IP) of the original designer. With the increase in deployment of FPGAs in modern embedded systems, the IP protection of FPGA has become a necessary requirement for many IP vendors. There have been already many proposals to overcome this problem using symmetric encryption techniques but these methods...
This paper presents the implementation of a configuration server for a SNTP synchronization platform which implements accurate synchronization solutions for Remote Terminal Units commonly used in industrial control processes. The configuration server provides settings to others platform devices using the BOOTP protocol and an interface that allow to administer the system. This environment requires...
This article presents and describes the implementation of an Ethernet communication platform for devices synthesized into Xilinx FPGAs. This platform provides a way to control programmable logic devices, as well as data communication using a standard network. The proposed solution is very complete and provides common services and protocols of TCP/IP stack, in order to provide maximum flexibility....
Control systems have been consistently evolving over time, with advances in processing capability in devices and controllers, as well as evolution of network capability. Process control systems are converging into a common model of integrated systems. The ability to easily integrate equipment control into higher-level end to end representations is becoming an imperative for manufacturing companies...
Traditional design can not choose appropriate CPU, peripherals and I/O module for different slave station of MECHATROLINK-III bus. Aimed at these issues, this paper proposes a slave station solution based on SOPC technology. To make I/O device as an example, a MECHATROLINK-III bus slave station is designed using SOPC, NIOS soft core and FPGA technologies. Data link layer peripherals, I/O module and...
With the growing diversity of malware, researchers must be able to quickly collect many representative samples for study. This is commonly achieved by harvesting the malware from honeypots: Insecure systems presenting a wide attack surface to the public Internet, aiming to attract attackers. However, software-based honeypots have both performance issues in light of 10+ Gb/s networks, as well as difficulties...
Packet classification involving multiple fields is used in the area of network intrusion detection, as well as to provide quality of service and value-added network services. With the ever-increasing growth of the Internet and packet transfer rates, the number of rules needed to be handled simultaneously in support of these services has also increased. Field-Programmable Gate Arrays (FPGAs) provide...
MPI is the traditional paradigm to parallelize applications for High Performance Computing environments. AzequiaMPI is an implementation of the MPI-1.3 standard. Its thread-based architecture enables it to run on high-end HPC machines as well as on embedded environments as soft-core processor in FPGAs. This article describes the experience of building a maintainable cluster of fourteen popular Xilinx...
This paper focuses on the implementation and performance analysis of a hardware/Software implementation of a Object Request Broker (ORB) to support a network of Distributed Smart Camera (DSC) systems. We present the overall system architecture as a part of the whole System on Chip (SoC) within FPGA. The performance analysis performed on a software as well as on our hybrid implementation is explained...
Malicious software has become a major threat to computer users on the Internet today. To combat it, security researchers need to gather and analyze many samples to develop proper defense mechanisms. The setting of honeypots, which emulate vulnerable applications, is one method of gathering attack code. In contrast to the conventional software-based honeypots, we have proposed a dedicated hardware...
In order to make full use of multi-IO signals to control equipments, a new type of universal IO controller based on Windows CE and C# is developed. It uses ARM9 as microprocessor, Windows CE as operation system and C# as programming language, and the multi-IO interfaces are extended by means of a simplified ISA bus and a FPGA chip. Two working modes are realized, local manual control and remote command...
PXIe protocol is a novel high-speed transmission bus protocol in industry. PXIe not only offers high performance up to 500MB/s bandwidth (4 lines), but also is completely compatible with PCI Express protocol. However, the current implementation in FPGA can not make full use of its advantages. The paper describes a direct memory access system to improve the real bandwidth of PXIe bus. For direct memory...
P2P protocol is widely used in many network applications. Recently, p2p traffic reserves a big part of total access bandwidth and may cause serious problems in EPON. In this paper, a new method to identify the p2p traffic based on the flow ID (five-tuple) is presented. We analyze the factors that influence identification accuracy, and then simulate accurate rate of the new method according to the...
The evolution of new services and the development of next generation networks is placing severe demands on networks. In order to support emerging services, it is clear that a higher degree of monitoring functionality is needed within networks. One approach is to use the programmability and performance of Field Programmable Gate Array (FPGA) technology to allow distributed monitoring but this present...
SPI is one of the most commonly used serial protocols for both inter-chip and intra-chip low/medium speed data-stream transfers. In conformity with design-reuse methodology, this paper introduces high-quality SPI Master/Slave IPs that incorporate all necessary features required by modern ASIC/SoC applications. Based upon Motorola's SPI-bus specifications, version V03.06, release February 2003, the...
As FPGAs become larger and more powerful, they are increasingly used as accelerator devices for compute-intensive functions. Input/Output (I/O) speeds can become a bottleneck and directly affect the performance of a reconfigurable accelerator since the chip will idle when there are no data available. While PCI Express represents the currently fastest and most expensive solution to connect a FPGA to...
The PROFINET IEC 61158 standardized Real Time Ethernet (RTE) protocol, Class C, has traditionally been limited by an artificially imposed 250us cycle time, originating from the requirement to ensure that full-sized legacy Ethernet frames can be transmitted in a single cycle through a network. Occasionally, especially in the case of high performance motion-control systems, this minimum cycle time is...
This paper introduces a SOPC high-speed interconnection platform based on FPGA convenient for integrate processing system with Ethernet. Embedded processor PowerPC405e, corporated with logic array, implement seamless connection with processing system, as well as gigabit Ethernet. It shows flexibility and efficiency through data storage and playback with NAS storage system.
The research conducted in this paper is aimed at developing a CDMA shared bus as the efficient communication architecture for SOC. The main benefits of using this technique relate to reduction of the number of wires on system bus which varies from 25% up to 81%, while the main disadvantage is increase of the latency of processor read and write operations. The structure of a CDMA wrapper as an interface...
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