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To recover the timing violations due to the delay variations after fabrication, delay tuning is promising. Delay tuning inserts programmable delay elements (PDEs) to circuits before fabrication and tunes their delays to recover the timing violations after fabrication. However, the yield of the circuits obtained by existing delay tuning methods is not improved enough and their power consumptions become...
Synchronous Switching Power Converters (SSPCs), which are suitable for fast-response high-efficiency applications, have become one of the research hot spots in recent years. A novel high-speed level shifter circuit with low power consumption is proposed in this paper, which is embedded in an integrated synchronous rectifier gate driver system. The proposed level shifter circuit consists of two parts:...
A novel self-turnoff control circuit for program process of one-time programmable (OTP) cell is proposed. Utilizing the current turnoff technology after the breakdown of OTP cell, it lowers the power consumption efficiently compared with traditional structures without turnoff mechanism. In addition, an additional delay circuit is also attached to the self-turnoff circuit to ensure the complete breakdown...
Ultra Low Power is the is one of the prominent technology in the VLSI Industry. One of the technique is used to improve Sub-threshold Logic Design. This technique is used to model the ultra-low power application design. This paper offers Sub-threshold logic for memory devices such as Static RAM and observed the power consumption (PC), leakage power(PL) and delay for different SRAM Bit models of 6T,...
A voltage-scalable bitline leakage current suppression technique with zero wake-up delay penalty is proposed to minimize the standby power consumption of low threshold voltage dynamic register files (RFs). Leakage currents via the pull-down paths of a wide fan-in dynamic logic gate are suppressed with a combination of fine-grained power gating and voltage lowering. A leakage-biased write bitline tracks...
A new nonlinear Time to Digital Converter (TDC) based on time difference amplification is the proposed. A new gain compensation method is presented to expand the DR of conventional ×2 Time Amplifiers (TAs). Instead of conventional gain compensation approach based on changing strength of current sources, the proposed technique uses current difference which results more stable gain over wider DR. In...
A low-power high-speed two-stage dynamic comparator is presented. The voltage fluctuation at the first stage of the comparator (pre-amplifier stage) is limited to Vdd/2. Therefore, the power consumption of the first stage which is the dominant part of the total power consumption is reduced. The output voltage of the first stage is kept above Vdd/2. As a result, during the comparison the second stage...
In this paper, we investigate and compare the performance of four different FinFET based multiplier topologies in terms of their leakage power, dynamic power, delay and power delay product at the transistor level. The multiplier topologies analyzed are Ripple Carry Array multiplier, Carry Save Array multiplier, Wallace Tree multiplier and Baugh-Wooley multiplier. The circuit simulations were performed...
A novel extended true single-phase clock-based (ETSPC) divide-by-3/4 prescaler is presented. Instead of the conventional technologies (i.e. transmission gates, logic gates), by using the pass transistor logic circuit, only two transistor are needed to realized the mode selection control. The operation speed is improved by reduction of the critical path delay between the ETSCP flip-flops. Since the...
Energy saving and quality of service are the most popular but contradictory criteria for resource allocation in IP-over-WMD network. Establishing of direct lightpath according to bypass architecture of IP-over-WMD network becomes reasonable when arriving traffic exceeds some threshold while under the threshold traffic have to be routed via compound path if it exists. On the other hand compound path...
The complete design and electrical characterization of a readout frontend for high luminosity pixel detectors is hereby presented. The design has been carried out in 28nm bulk-CMOS technology. The selected technology process shows significant advantages in terms of radiation hardness, faster/low-power digital signal processing and whole chip area reduction. Nonetheless, it is challenging in terms...
This paper presents a high resolution tunable ring oscillator type TDC (Time to Digital Converter). The proposed structure uses 2 ring oscillators composed of 8 differential inverters. Can be activated by selecting one of the three resolution in the structure, and can be selected in a ratio of 15/16, 13/32, 63/64, depending on fast and slow of the differential inverter delay. Also to increase the...
This paper presents a type-I digital ring-based PLL with wide loop bandwidth to lower the ring oscillator's noise contribution. The in-band noise is addressed using a SAR-ADC-based sampling phase detector (SPD). A stacked reference buffer is also introduced to reduce the transient short-circuit current for low power and low reference spur. The loop delay due to the D flip-flops at filter's output...
Due to technology scaling, radiation induced errors which cause a double node upset (DNU) have become more common in data storage elements. All current designs either suffer from high area and performance overhead or are vulnerable to an error after a DNU thus making them unsuitable for clock gating. A novel latch design is proposed in which all internal and external nodes are capable of recovering...
A circuit architecture to generate differential CMOS quadrature (I/Q) local oscillator (LO) signals from a differential input at the same frequency is presented. The phase accuracy of the proposed architecture relies on the matching of two delays and linear phase interpolation. The feasibility of this approach is demonstrated by implementing an I/Q generator covering the operating frequency range...
In this paper, we present and compare the design and the performances of ten different implementations for a 16-bit adder in a 180nm CMOS standard-cell technology. Ripple carry adder, increment adder, triangle adder, uniform and progressive carry select adder, uniform and progressive carry bypass adder, conditional adder, ripple carry look ahead adder and hierarchical carry look ahead adder are taken...
Modern on-chip networks (NoCs) rely on virtual channel (VC) flow control to allow effective utilization of link bandwidth at the cost of more power and longer per-hop latency. Despite many existing optimization techniques for NoCs under VC flow control, we take a further step on questioning its necessity. Our finding is, when the network is not busy, circuit-switching (CS) may already satisfy the...
We propose a non-redundant Flip-Flop (FF) with stacked transistors based on Adaptive Coupling Flip-Flop (ACFF) with lower power consumption in a 65 nm Fully Depleted Silicon On Insulator (FDSOI) process. The slave latch in ACFF is much weaker against soft errors than the master latch. We design several FFs with stacked transistors in the master or slave latches. We investigate radiation hardness of...
In this work, the performance of ring counter is improved using pulsed latch technique. In high speed and low power VLSI applications where heavy pipelining is used, there is requirement of low power edge triggered flip flops. The migration from flip flop to pulsed latch has become great success in low power VLSI application. The proposed circuit has been designed using Cadence Virtuoso in 90 nm CMOS...
Cloud computing is an emerging technology to increase the efficient utilization of huge collection of high-end resources at low cost. One of the major problems associated with cloud environment is that these high-end systems need huge power consumption. Several methods are proposed and available for reducing the power consumption in datacenters. But most of these methods do not meet the Quality of...
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