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This work compares many different transistors arrangements of XOR logic gates under PVT variability effect in 16nm device technologies: CMOS Bulk and FinFET. The objective is to identify how these two different device technologies deal with PVT variability effects on performance and power characteristics. Ten different XOR topologies are evaluated. The results show different transistor arrangements...
Achieving energy efficiency has recently become an essential aim of networking research due to the ever increasing power consumption and CO2 emissions generated by large data networks. For this problem, the emerging paradigm of Software-Defined Networks (SDN) can be seen as an attractive solution. In these networks an energy-aware routing model could be easily implemented leveraging the control and...
Mobile-edge computing (MEC) has recently emerged as a promising paradigm to liberate mobile devices from increasingly intensive computation workloads, as well as to improve the quality of computation experience. In this paper, we investigate the tradeoff between two critical but conflicting objectives in multi-user MEC systems, namely, the power consumption of mobile devices and the execution delay...
We tackle a production scheduling problem in a manufacturing system. The aim is to design an efficient exact method and find a trade-off between tardiness, storage and energy costs described by a piecewise-linear function. Therefore, we propose two time-based MILP formulations. The first one is precedence-oriented and the second is storage-oriented. These two formulations are compared and tested on...
In this paper, we construct an analytical design framework for energy efficient scheduling for delay-constrained spectrum aggregation (ESSA), where the practical hardware limitations on SA capability bring various technical challenges. Specifically, the conventional water-filling power control cannot be adopted over all the channels, and the delay-aware scheduling solution should interact with the...
In this paper, a high-speed and low-power latched comparator in a 65-nm CMOS process is presented. In our proposed structure, a latched circuit with an adjusted delayed-clock with no static power consumption is added to the conventional latch-type comparator in order to enhance the clock frequency and reduce the power consumption and the delay time. Therefore, the maximum clock frequency of our proposed...
The conventional NOR-based decoders are one ofthe fastest dynamic decoder circuits employed in microprocessors. However, they suffer from a huge amount of power dissipationresulting from the presence of short circuit paths betweenthe supply and the ground through pull-down network. Twodecoder designs with a novel selective precharge circuit have beenproposed in this paper using 32nm FinFET technology...
There is no doubt that static CMOS circuits are the best candidate for low-power and high-packing density applications. However, its performance degrades with increasing the fan-in. In this paper, a novel fast CMOS circuit that is based on a current race is presented and compared with the conventional CMOS logic from the points of view of area, power consumption, and average-time delay. The scheme...
In order to optimize the power consumption and improve the energy efficiency, the smart grid (SG) provides reliable, efficient and secured electrical power generation and distribution. Smart grid aims to manage and control the consumer demand and provide the needed power. Thus, in smart grid architecture, the information about power supply must be known, in advance, by the operator. This information...
This work explores challenges in silicon integration of scalable high-throughput “Wireless Fiber” links that exploit the increase in spatial and spectral degrees of freedom at higher carrier frequencies due to LOS MIMO spatial multiplexing and higher bandwidths. In order to utilize these increased degrees of freedom, however, hardware must scale in dynamic range, speed and number of antenna elements...
Many digital Signal processing (DSP) applications requires complex arithmetic operation which is carried by multiplier and adder units. Multiplication operation can be done as a successive addition which introduces delay in the processing. In which implementation of this technique with delay constraints leads to more challenging. Because the internal modules generate delay in propagation of processed...
A compact system for on-chip supply current wave-form reconstruction and power estimation is presented. The system, comprising a programmable current load, a sampling comparator and processing logic, is implemented in a 28nm FD-SOI system-on-chip (SoC) to monitor the supply of a digital processor generated by a switched-capacitor DC-DC converter. The monitoring system is able to reconstruct the rippling...
Heterogeneous networks (HetNets) are considered a key enabling technology to provide high capacity for next generation, also known as fifth generation (5G), networks. However, in order to efficiently exploit the advantages of HetNets and strive towards high network efficiency, efficient user equipment (UE) association is decisive for targeting network performance goals. Therefore, in this work, user...
Cloud computing controls the increasing energy consumption of applications by consolidating them in shared servers through virtualization. This technique can be greatly improved and complemented by choosing an optimal data center for each Virtual Machine (VM). That dynamic optimization problem was stated as a Mixed Integer Linear Programming (MILP) model that minimizes operational expenditures, while...
The IEEE 802.3az standard, known as Energy Efficient Ethernet (EEE), is one of recent efforts to improve energy efficiency in communications. However, EEE may not achieve good energy efficiency on some traffic patterns. Coalescing techniques were proposed to solve this problem, but their implementations typically employ a simple polity and need further optimization. Adaptive interrupt coalescing (AIC)...
In next generation networks, ultra-dense small cell networks are emerging to deal with exponential data traffic increasing. With the deployment of small cells (SCs) becoming increasingly dense, these cells may be under-utilized during quite a few period of time. Depending on this circumstance, we aim to maximize the network energy efficiency by deactivating such under-utilized cells, subjecting to...
This paper presents a novel technique based on System Verilog assertions to optimize the consumed power of RTL designs. The proposed technique helps the designer to enhance his RTL code towards achieving low power design. The designer codes the proposed technique according to the design specifications and integrates the coded technique into his test bench. The coded technique generates directive massages...
Network-on-Chip technology has become very popular in the recent decade to address the scalability issue in multi-core processors. Developing the inter-connection network improves the performance of multi-core systems at the cost of additional power and design complexity. Power-gating of router buffers as the most power consuming part of Network-on-Chip has been proposed recently to reduce the static...
Packet-switched Network-on-Chip (NoC) is the shared global communication infrastructure for future large-scale chip multi-processors (CMPs). Recently, Single-cycle Multi-hop Asynchronous Repeated Traversal (SMART) on repeater-inserted wires to reduce packet delay was proposed. But current NoC with SMART support adds complexity to conventional routers and incurs high power consumption. In this paper,...
4×4 Vedic multiplier using domino logic is proposed in this paper. The designs are implemented in GPDK 90nm technology on cadence virtuoso tool using spectre simulator. Multiplication is a fundamental operation, which is widely used in many digital signal processing systems, multimedia applications, computers and many digital systems. Power and delay are two important design constraints but there...
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