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Silicon photomultipliers (SiPMs) are meant to substitute photomultiplier tubes in high-energy physics detectors and nuclear medicine. This is because of their —to name a few interesting properties— compactness, lower bias voltage, tolerance to magnetic fields and finer spatial resolution. SiPMs can also be built in CMOS technology. This allows the incorporation of active quenching and recharge schemes...
We study the impact of asymmetric loading on the power saving performance of EPON networks. It is generally observed that asymmetric loading often leads to reduced network performance compared to that from symmetric loading. For such network, an adaptive bandwidth assignment scheme according for traffic load can be set to meet the target of delay performance or power saving effect.
In this work we present the design of a digitally controlled ring type oscillator in 0.5 μm CMOS technology for a low-cost and portable radio-frequency diathermy (RFD) device. The oscillator circuit is composed by a low frequency ring oscillator (LFRO), a voltage controlled ring oscillator (VCRO), and a logic control. The digital circuit generates an input signal for the LFO, which generates a voltage...
In this paper, four different single ended delay cells based ring oscillators have been presented. Output frequencies of ring oscillators have been controlled by varying the supply voltage 1.4V to 3.0V. The active load concept has been used in proposed circuits. First design shows frequency variation in the range [4.50–1.40] GHz with phase noise −87.79dBc/Hz @1MHz in saturated load. Second design...
Active rectifier with comparators (CMPs) is often used in wireless power transmission (WPT) systems. However, it suffers from low power conversion efficiency (PCE) in light load condition and multiple pulse problem (MPP) due to the CMPs with delay compensation. In this paper, a novel active rectifier with delay time controller is proposed to solve both issues. A current control delay line (CCDL) is...
This paper presents a versatile, FCC compliant ultra-wideband impulse radio transmitter front-end (TFE) that performs well at a wide range of pulse repetition rates up to 105 MHz. The TFE delivers 2.2 pJ pulses with 6.7 % efficiency at 3.8 GHz center frequency. The leakage power is 180 nW from a 1.2 V supply. The TFE operates robustly with a variety of power sources, including a 6.5 cm2 photovoltaic...
For pursuing the high speed information transmission, the design and research of the high speed SerDes circuit are actively developing now. Due to the requirements for long transmission path, intensive equalization and high speed transmission circuit testing function, two high speed SerDes circuits are designed and fabricated based on 130nm SiGe BiCMOS technology. One is for the research of the equalization...
A 40 Gb/s PAM4 receiver with novel digital clock and data recovery (CDR) and one tap decision feedback equalizer (DFE) has been presented. Without sophisticated transition detection and selection modules, the proposed CDR utilizes three bang-bang phase detectors sampling all the transitions to detect the phase error between the data and clock, achieving larger transition density and CDR bandwidth...
Arithmetic Logic Unit plays a vital role in the central processing unit of the computer system. Addition is considered to be a primary part in the ALU. Power and speed are the major parameters to be kept in mind for designing an adder. Because of carry propagation, complexity and delay gets introduced in the adder circuit due to which addition, subtraction and multiplication obtains delay in the Arithmetic...
In this paper, we aim to obtain the optimal delay-power tradeoff and the corresponding optimal scheduling policy for arbitrary i.i.d. arrival process and adaptive transmissions. The number of backlogged packets at the transmitter is known to a scheduler, who has to determine how many backlogged packets to transmit during each time slot. The power consumption is assumed to be convex in transmission...
Heterogeneous small cell network is a promising technique in the next generation mobile communications. Many works have been studied in small cells, including resource allocation and interference mitigation, but most studies didn't consider the quality-of-service (QoS) and power consumption. This paper focuses on the power allocation based on non-cooperative scheme to mitigate the interference and...
In this paper, we analyzed near-threshold-voltage (NTV) CMOS circuits with various body bias and proposed an NTV adder design with dual body bias. By adopting different body bias in the same time, adder delay and leakage power can be reduced. Also, the critical path is optimized to achieve better energy efficiency. The performance analysis are all performed under TSMC 90nm CMOS process with Monte...
Rising energy costs and the push for green computing have inspired a lot of research effort towards energy efficient computing. Incorporating low energy sleep states in server farms is one of the proposed solutions. This paper studies the trade-off between energy and performance that is inherent in such solutions using the popular cost metric Energy-Response-time-Weighted-Sum (ERWS). We apply the...
Multiple-valued logic (MVL) has potential advantagesfor energy-efficient design by reducing a circuit complexity. Because of physical device and circuit realization issues, however, there are relatively small number of researches on MVL circuitdesigns. We design a novel ternary multiplier based on a ternaryCMOS (T-CMOS) compact model. To estimate performance andenergy efficiency of our ternary design,...
Full adder circuit is one of the most important digital functional block used in ALU. This paper presents a novel design of 8T full adder. The 8T full adder is designed on basis of a new logic 3T XOR and 2:1 multiplexer, in total of 8T. Compared to other existing full adders of 10T, 14T. There is significant improvement in power consumption, delay and power-delay product. For a supply voltage of 1V...
Carry Select Adder (CSA) is faster than any other adders used in many data-processing processors to achieve arithmetic functions speedily. By observing the structure of the CSA, it is clear that there is way for reducing the delay and power consumption. This work uses a sophisticated and efficient gate-level modification to significantly reduce the delay and power of the carry select adder. From the...
Adders are basic building blocks of any processor or data path application. Adders are not only used for addition, but for many other functions such as subtraction, multiplication and division. For fast arithmetic operations the use of high speed adders is a requirement. Therefore, design of high speed adders with minimum power consumption are essential for the design of high speed arithmetic units...
Carry Select Adder (CSA) architectures are proposed using parallel prefix adders. Instead of using dual Ripple Carry Adders (RCA), parallel prefix adder Brent Kung (BK) adder is used to design Regular Linear CSA. Carry Select Adder is a compromise between RCA and CLA in term of area and delay. Delay of RCA is large therefore we have replaced it with parallel prefix adder which gives fast results....
Neural networks are widely used in various fields due to their superior learning ability. Concurrent with the increase in their popularity, the rise of Big Data has resulted in increased computational requirements and processing power. To meet the requirements of real-time learning and classification, the process of finding the maximum value proves to be the performance bottleneck, and therefore needs...
The rapid development of the smartphones penetrated in every aspect of daily life starting from the health care, education, economics, social life etc. The prominence of the smartphones comes due to their size and connectivity, size made them the first handy personal computer available for 24\7 to the users. Unfortunately, the power of these smart devices and applications are limited and dependent...
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