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Decreasing hardware reliability makes robust firmware imperative for safety-critical applications. Hence, ensuring correct handling of errors in peripherals is a key objective during firmware design. To adequately support robustness considerations of firmware designers during implementation, an efficient qualitative fault injection method is required. This paper presents a high-speed fault injection...
Recently, we must use the various scan test techniques for various purposes, for example, compression scan or LBST for mass-production test, LBIST for field test, legacy scan for fault diagnosis, and so on. Moreover, the number of the available external scan pins is different in each test process, for example, the parallel test process has a low pin count, the assembled chip test process has several...
Scan chain diagnosis plays an important role in silicon debug and yield ramp-up since 10% to 30% of chip failures are caused by scan chain failures. Failure data collected on testers is limited by buffer sizes to capture the failing responses from scan chains, especially since scan chain failures produce a large amount of failing responses. In this paper, we propose a new pattern selection method...
In the recent time we have witnessed the expansion of Near Field Communication (NFC). NFC is wireless short-range communication technology with increasing number of applications. Mo1bile payment is the most critical and the most important application of the NFC, which needs to be tested properly. The use of tools that help and improve the testing of NFC makes the testing process considerably easier...
For the requisite of verifying the MIKME advanced microphone during serial production, an automated test system for hardware testing was developed. The system, that comprises a specially designed test fixture — bed-of-nails, the PXI instrumentation and a LabVIEW application, is presented in the paper with all of its features related to the MIKME product. The proposed solution is up to 20 times faster,...
We present a platform to allow up to 50000 students to simultaneously collect and learn from their personal activity, transportation, and environmental data. The main goals that we met during the design of our sensor platform were to: 1) be low cost; 2) remain powered for the duration of the data collection campaign; 3) robustly sense a wide range of environmental parameters; and 4) be packaged in...
For those responsible for the design and implementation of a SpaceFibre network it is essential to be able to capture and view the traffic on a SpaceFibre link in order to help validate the link is operating as expected and debug the link should any unexpected behaviour be observed. STAR-Dundee Ltd have developed hardware independent SpaceFibre Link Analyser software for this purpose. This paper describes...
Compliance or conformance testing is basically a kind of an audit which is performed for the system to check whether all the specified standards are met or not. Implementation of conformance testers for the communication protocols is an important task, which is being solved in the majority of industrial companies that develop the communication equipment. On-board equipment always needs a proper testing...
Even though research on autonomous robots and human-robot interaction accomplished great progress in recent years, and reusable soft- and hardware components are available, many of the reported findings are only hardly reproducible by fellow scientists. Usually, reproducibility is impeded because required information, such as the specification of software versions and their configuration, required...
We propose a new method of determining an effective ordering of regression test cases, and describe its implementation as an automated tool called SuiteBuilder developed by Westermo Research and Development AB. The tool generates an efficient order to run the cases in an existing test suite by using expected or observed test duration and combining priorities of multiple factors associated with test...
This paper presents novel architectures for machine learning based classifiers using stochastic logic. Two types of classifier architectures are presented. These include: linear support vector machine (SVM) and artificial neural network (ANN). Stochastic computing systems require fewer logic gates and are inherently fault-tolerant. Thus, these structures are well suited for nanoscale CMOS technologies...
Based on hardware and software integration testing and model driven testing binding requirements, we propose a model based on the needs of embedded software driver initial framework to analyze and identify the needs of embedded systems hardware and software object creation object interaction model, then the model analysis and testing constraints and on the basis of test scenarios, and then establish...
An unconventional software testing method, fault injection based on fault model, is enhanced to improve the software reliability testing and measurements. Dynamic fault models for injecting faults through software are investigated and reported in this paper including memory faults, CPU faults and communication fault models. Dynamic fault models can be used to simulate influences which are caused by...
This paper points out the problems of digital relay protection tester and the new requirements of relay protection testing in smart substation, combining the key technology of automation relay protection tester and takinG full advantage of the IEC 61850 standard, such as the unified protocol, the configurable model file, the specification of State Grid's “Six Reunification” as well. In this paper,...
With the evolution of power system components and structures driven mainly by renewable energy technologies, reliability of the network could be compromised with traditional control methodologies. Therefore, it is crucial to thoroughly validate and test future power system control concepts before deployment. In this paper, a Controller Hardware in the Loop (CHIL) simulation for a real-time distributed...
This paper presents our recent work on the analyses of smart phone sensor data collected for the human activity recognition (HAR), with the objective to develop more accurate activity recognition systems independent of smart phone models. We identify the multi-device scenario and present the impairments of different smartphone embedded sensor models on HAR applications. Outlier removal, interpolation,...
The rapid development in the modern technology and its widespread utilization in number of applications brings in new challenges that need to be addressed. Security is one of such challenges that has grown into a major concern over the years. Periodically new incidents of data and system breaches are reported. For this purpose, usually different side channels in the system are being exploited by the...
The results of development of multi-core recurrent dataflow architecture (MRDA) focused on effective implementation of parallel digital signal processing (DSP) algorithms are being presented. All stages of MRDA development are integrated into a single iterative design cycle including mathematical modeling tools (imitational model); hardware modeling tools (VHDL-model); FPGA prototype and tools for...
With the ever growing complexity of hardware designs, their functional verification has become quite a challenge. Despite other techniques like emulation and formal verification methods, simulation continues to be the most common and primary technique to functionally verify the hardware design written in Verilog. Due to the limited computational resources, exhaustive testing of the present-age complex...
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