The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
An ultra-light-weight PRINCE cryptographic processor is developed. A fully-unrolled differential-logic architecture saves delay, energy, and area (i.e. hardware weight) of XOR as a dominant cipher component. An S-box is composed only by four kinds of compact composite gates and a replica-delay-based transition-edge aligner prevents glitches accumulated in the long unrolled combinational-logic data...
This paper presents an ultra-high-speed/area-efficient Polar encoder design with very high system throughput for emerging next-generation 5G applications. In a demonstrated design example, the proposed hardware architecture is mainly based on 16-parallel radix-2 processing engines. An 8192-point Polar encoder is designed and synthesized with TSMC 40-nm CMOS technology, operating at clock frequency...
The article describes a low-cost and open IoT platform for rural applications in developing countries. Using the latest low-power, long-range radio technologies and off-the-shelves components, the platform can be quickly deployed and customized for a large variery of rural applications. We present in the article how a low-cost IoT collar device especially addressing the cattle rustling issues can...
Error-tolerance is a notion that focuses on evaluating the acceptability of errors by considering the insensitivity of human beings to minor vibrations in multimedia applications. In this paper we will show that this notion can relax the functional test requirements of a target circuit. Rather than finely grading the quality of the output results as conventional methods do, we only need to decide...
In this paper, we study a resource granularity effect on the optimal resource assignment of MME and S/P-GW in a single vEPC server. We distinguished communications of M2M devices and smartphones and modeled the vEPC server by using queueing theory. Numerical analysis under a fixed number of hardware resources of MME and S/P-GW is done for various resource granularities of the vEPC server. The evaluation...
In order to tolerate faults that emerge in operating Networks-on-Chip, diagnosis techniques are employed for fault detection and localization. On various network layers, diverse diagnosis methods can be employed which differ in terms of their impact on network performance (e.g., by operating concurrently versus pre-empting regular network operation) and the quality of diagnostic results. In this contribution,...
Recurrent Neural Networks (RNNs) have the ability to retain memory and learn from data sequences, which are fundamental for real-time applications. RNN computations offer limited data reuse, which leads to high data traffic. This translates into high off-chip memory bandwidth or large internal storage requirement to achieve high performance. Exploiting parallelism in RNN computations are bounded by...
Recently, due to the increase of outsourcing in IC design, it has been reported that malicious third-party vendors often insert hardware Trojans into their ICs. How to detect them is a strong concern in IC design process. The features of hardware-Trojan infected nets (or Trojan nets) in ICs often differ from those of normal nets. To classify all the nets in netlists designed by third-party vendors...
This paper presents a high-throughput hardware architecture for the HEVC intrapicture prediction targeting the processing of UHD 8K (7680×4320 pixels) videos at 120 frames per second. The proposed design supports all intra prediction modes and all block sizes. It implements an internal mode decision algorithm that is more hardware friendly than RMD at the cost of a negligible 0.17% BD-rate impact...
This paper presents a technique for addition/subtraction in the Logarithmic Number System (LNS) which is based on Floating Point addition/subtraction, specifically on fractional normalization (FN). The proposed technique is analyzed and compared with two other methods for addition/subtraction using 11- and 17-bit word lengths. The results are demonstrated by evaluating complexity and performance of...
Text analytics has become increasingly important in the past few years because of the substantial growth in the amount of research, business, and government needs. An efficient text analytics system is likely to require high-powered regular expression matching (REGEX), as REGEX operations dominate the whole execution time. Some approaches have exploited the parallelism of graphic processing units...
Hardware Trojan detection, which is very important to the chip security, has drawn more and more attention in both academia and industry. In this paper, we propose a novel hardware Trojan detection scheme named HTChecker, which detects hardware Trojans with subgraph isomorphism based on static characteristics of Trojans. Unlike other schemes, HTChecker pay more attention to preventing the replication...
A novel Denial-of-Service attack for Networks-on-Chip, namely illegal packet request attack (IPRA), has been proposed and measures to mitigate the same have been addressed. Hardware Trojans, which cause these attacks, are conditionally triggered inside the routers at the buffer sites associated with local core, when the core is idle. These attacks contribute to the degradation of network performance...
In this paper, two kinds of simplified cell structures for low voltage noise immunity and a hybrid Markov Random Field probabilistic-based circuit design technique are proposed to reduce the hardware overhead and improve the noise immunity. To demonstrate the proposed technique, four kinds of test chips with an 8-bit carry lookahead adder (CLA) are fabricated in a 130nm CMOS technology. Measurement...
This paper shows that threshold logic functions can be implemented in CMOS-based current mode logic with reduced transistor count when the input weights are not restricted to be integers. A novel implementation of non-integer weights is proposed. Experimental results show that the transistor count reduction results in significant reduction in power dissipation and delay.
A Physical Unclonable Function (PUF) is often used to uniquely identify an integrated circuit by extracting its internal random differences using so-called Challenge Response Pairs (CRPs). As CRPs include unique information about the underlying hardware variations, PUF design is a promising approach to provide authentication and IP-protection capabilities. In this paper, an XOR-gate-based configurable...
A low-end embedded platform for Internet of Things (IoT) often suffers from a critical trade-off dilemma between security enhancement and computation overhead. We propose PUFSec, a new device fingerprint-based security architecture for IoT devices. By leveraging intrinsic hardware characteristics, we aim to design a computationally lightweight security software system architecture so that complex...
The urgent requests to protection integrated circuits (IC) and hardware intellectual properties (IP) have led to the development of various logic obfuscation methods. While most existing solutions focus on the combinational logic or sequential logic with full scan-chains, in this paper, we will revisit the security of sequential logic obfuscation within circuits where full scan-chains are not available...
Scan based diagnosis plays a critical role in yield enhancement of sub-nanometer technology based chips. However, the scan chain itself can be subject to defects due to the large logic circuitry associated with it which constitute a significant fraction of total chip area. In some cases, it has been observed that scan chain failures may account for 30% to 50% of chip failures. Hence, scan chain testing...
Feature-based hardware Trojan (HT) detection method has gained its popularity recently because it does not need any test patterns or golden models. However, HT feature database is to be expanded due to emergence of new HTs. We present in this paper a method based on the structural characteristics of single-triggered HTs. Various structure templates are extracted from gate-level netlists, and a scoring...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.