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In this paper, ultrascaled n- and p-channel Si nanowire field-effect transistors (NW FETs) with [100], [110], and [111] as channel orientations are simulated in the presence of electron-phonon scattering using a sp3d5s* tight-binding approach and confined phonon dispersions. The low field mobility, the injection velocity, and the ballisticity of these devices are extracted and compared to n-type InAs...
Graphene, a two-dimensional carbon form with the highest intrinsic carrier mobility and many desirable physical properties at room temperature, is considered a promising material for ultrahigh speed and low power devices with the possibility of strong scaling potential due to the ultra-thin body. (Fig. 1) [1-3] Here IBM reports progress in graphene nanoelectronics, synthesizing wafer-scale monolayer-controlled...
Silicon nanowire transistor with side-gate and back-gate has been fabricated by electron beam lithography combined with dry oxidation on a doped silicon-on-insulator wafer. The effects of back-gate and side-gate on the properties of single electron transport were investigated by measuring the channel current as function of the applied gate voltages. The tunable single electron effect and Coulomb oscillations...
We successfully achieved the reduction of the parasitic resistance and the mobility enhancement in Si nanowire transistors (NW Tr.) by raised source/drain extensions with thin spacer (<;10nm) and by stress induced from heavily-doped gate. Id variations are suppressed by the spacer thinning. By adopting <;100> NW channel instead of <;110> NW, Ion = 1 mA/μm for Ioff = 100 nA/μm is achieved...
A fast integrated gate driver with amorphous silicon thin film transistor (a-Si:H TFT) is proposed in this paper. To improve the circuit speed, a new input scheme is designed to provide a full scale pre-charge voltage. So the loss of pre-charge voltage, a challenge in the conventional designs, is avoided. Simulations show that the proposed gate driver has a much improved driving speed in comparison...
This paper presents a new poly-Si thin film transistor (TFT) pixel circuit for active-matrix organic light-emitting diode (AMOLED) displays. The pixel circuit has a simple four-transistor configuration and is controlled by two adjacent gate scan pulses, allowing a small circuit area and simple driving scheme. Simulation results show that this pixel circuit can provide the OLED with a current non-uniformity...
Capacitance-voltage (C-V) and frequency dependent conductance-voltage (G-V) measurements have been carried out to investigate the charging and discharging effect induced by interface states and nanocrystalline Si (nc-Si) in floating gate MOS structures. Distinct conductance peaks are observed in the G-V curves for the floating gate with and without nc-Si dots. Based on the calculation of interface...
A new type of polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with self-aligned metal electrodes (SAME) is systematically characterized. New device features different from conventional poly-Si TFTs are found, and are attributed to the presence of Schottky barriers at the channel ends.
In this paper, the impacts of diameter-dependent annealing (DDA) effect on nanowire S/D extension random dopant fluctuations (SDE-RDF) in silicon nanowire MOSFETs (SNWTs) are investigated, in terms of electrostatic properties, source/drain series resistance (RSD), and driving current. The SDE-RDF induced variations of threshold voltage (Vth) and DIBL in SNWTs with different diameters are found to...
In this paper we overview recent attempts at co-integrating silicon nano-electro-mechanical systems (NEMS) with nanoelectronic devices aiming to add more functionalities to conventional electronic devices in `More-than-Moore' domain and also explore novel operating principles in `Beyond CMOS' domain.
In this paper, we propose a junctionless vertical MOSFET (JLVMOS) based on bulk-Si wafer. According to the numerical simulations, the proposed JLVMOS can get a steep subthreshold swing (S. Swing), reduced DIBL, and higher ION/IOFF ratio, in comparison to a junctionless planar SOI MOSFET. This is because the vertical double-gate (DG) structure truly helps reduce the short-channel effects (SCEs). More...
A new method for extraction of series resistance is proposed for poly-Si thin-film transistors. In this method, the extraction procedure is insensitive to the variation in effective channel length and device mobility, since both quantities are included in a single extracted parameter. The method has been successfully applied to a group of poly-Si TFTs with mask channel length from 2 to 30μm. Compared...
The nc-Si nonvolatile memory devices with high performance have been fabricated by using general CMOS techniques. High resolution transmission electronic microscope (HRTEM) shows that the average size of nc-Si is 8 nm and its density is 3×1011/cm2. The performance of programming/ erasing and retention time is mainly depending on the quality and thickness of tunnel layer and control layer. The results...
High-quality germanium oxynitride (GeON) gate dielectrics for Ge-based metal-oxide-semiconductor (MOS) devices were fabricated by plasma nitridation of ultrathin thermal oxides on Ge(100) substrates. Although ultrathin oxides with abrupt GeO2/Ge interfaces can be formed by conventional dry oxidation, air exposure results in serious electrical degradation. It was found that plasma nitridation forms...
CMOS utilizing high mobility III-V/Ge channels on Si substrates is expected to be one of key devices for high performance and low power advanced LSIs in the future. In addition, the heterogeneous integration of these materials on the Si platform can provide a variety of applications from high speed logic CMOS to versatile SoC chips, where various functional devices can be co-integrated. In this presentation,...
Normalized Differential Conductance Spectroscopy (NDCS) has been used to investigate the tunneling properties of post soft breakdown SiO2. It is shown that the NDCS is capable of separating various components of tunneling current and determining its corresponding tunnel constants of post SBD SiO2. Therefore, the most important tunneling parameters: the effective mass of tunneling electron in SBD SiO...
The low-frequency (LF) noise behaviour of pMOSFETs fabricated in strained Ge (sGe) and reference thick Ge-on-Si epitaxial layers has been compared. As is shown, the LF noise in the subthreshold regime is higher for the reference devices compared with the sGe, while in strong inversion, similar noise levels are achieved. The better noise performance in weak inversion is related to the lower density...
A simple top down method to fabricate an array of vertically stacked nanowires is presented. By taking advantage of the non-uniformity of the Inductive Coupled Plasma (ICP) etching process to form a scalloped sidewall followed by a subsequent stress limited oxidation step, a narrow silicon fin can be vertically patterned to form stacked nanowires with different cross-sectional shapes. The stacked...
Continuously down-scaling EOT and improving mobility are required for CMOS device. Small 0.6~1 nm EOT and low Vt of ~0.15 V are achieved in CMOS by using higher κ gate dielectric and novel process. The ultimate EOT scaling is limited by the inserted ultra-thin SiON interfacial layer in high-κ/Si to reduce the mobility degradation. Further mobility improvement is obtained by using Ge channel MOSFET...
The DC and analog/RF performance of p-channel Schottky barrier Si and Ge nanowire transistors are simulated and some impact factors are studied. The results suggest that 100meV and 50meV are the most optimized Schottky barrier height for intrinsic gain and cutoff frequency respectively. Thinner nanowires enhance the drivability of silicon devices while impair that of germanium devices. With gate length...
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