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A 5th-order Chebyshev active RC complex filter for wireless sensor networks with automatic frequency tuning is presented in this paper. This filter is synthesized from 5th-order low-pass LC prototype, and designed using leapfrog structure. An automatic frequency tuning is used to prevent the deviation of the RC constant of the filter. This filter is fabricated in TSMC 0.18μm CMOS process. The measurement...
A biomedical electronics interface to detect heart signals is presented including a reconflgurable full differential fifth-order Bessel Gm-C filter and a 12 bit low-power fully differential successive approximation register analog-to-digital converter (SAR ADC). The total fully differential structure reduces the input signal noise and distortion effectively. A switch array is used in Gm-C filter to...
This paper presents the concept and design of a wideband merged LNA and mixer covering the frequency range from 2GHz to 10GHz using a standard 0.18-μ m CMOS technology. Gm-boosting and current bleeding techniques are adopted to make the proposed single stage merged LNA and mixer topology suitable for high conversion gain, low noise and low power consumption operation. A proposed current peaking technique...
This paper presents a 0.9GHz-10GHz Ultra Wideband Low Noise Amplifier (LNA) designed for software-defined-radios (SDR). Capacitive cross coupling (CCC) is used at both input stage and cascade stage for wideband input impedance matching and small noise figure (NF). A combination of inductor peaking load and series inductor between the cascade stages of LNA is employed for a flat gain and enhanced input...
This paper presents a group-selected (GS) and gain controllable (GC) active mixer designed for ultra-wide-band (UWB) receiver. The double-balanced Gilbert-type configuration, current bleeding technique and resonating technique for tail capacitance are incorporated in the proposed mixer. A switched capacitance network (SCN) is used to control the resonant frequency of the tail capacitance for the group...
A high gain and high linearity down conversion mixer combining low phase noise oscillator based on CMOS 0.18μm process is presented in this paper. To enhance the conversion gain and to reduce power consumption, the proposed mixer employs gm-boosted technique. The proposed circuit achieves simulated conversion gain of 18.07dB, input third-order intercept point (IIP3) of -5.85 dBm and noise figure of...
In this paper, a programmable gain amplifier (PGA) for wireless sensor network (WSN) is proposed and implemented using 0.18 μm CMOS process. A fully differential feedback configuration is adopted, and the variable gains are achieved by switch controlled resistor (SCR) network. DC feedback technique is also utilized to eliminate the DC offset. SCR network layout design is essential to maintain the...
A 10-Gb/s transimpedance amplifier (TIA) for the parallel optical receiver module is realized in 0.18-μm CMOS technology. The proposed TIA employs a regulated cascode (RGC) input structure and adopts active inductor peaking and feedback techniques to enhance the bandwidth. Besides, a noise optimization is processed. The TIA provides a conversion gain of 50 dBΩ and 3-dB bandwith of 7 GHz. The measured...
A fully integrated double frequency differential LC voltage controlled oscillator (VCO), used in the frequency synthesizer of 2.4GHz IEEE802.15.4/ZigBee Wireless Sensor Network (WSN), is designed and implemented based on TSMC 0.18μm RF CMOS process with low power dissipation and wide tuning range. The core circuit adopts complementary differential negative resistance LC oscillator structure and is...
In this paper, a low dropout voltage regulator (LDO) for radio frequency (RF) circuits of IEEE802.15.4/ZigBee wireless sensor network (WSN) is proposed and implemented by using TSMC 0.18μm CMOS process. Bandgap reference circuit startup problem and stability of LDO are key problems of LDO circuit design, and their reasonable solutions are given in this paper. Chip measurement results demonstrate that...
A frequency synthesizer capable of generating all the 14 sub-band carrier frequencies in 3.1~10.6 GHz band for multiband OFDM ultra-wideband (MB-OFDM UWB) transceivers is proposed. It is composed of a phase-locked loop (PLL), two singlesideband (SSB) mixers, and two multiplexers (MUXs). Switched-cascode architecture with switched LC tanks is adopted in the multiplexers to ensure fast switching. A...
A fully integrated double frequency differential LC voltage controlled oscillator (VCO), used in the frequency synthesizer of 2.4GHz IEEE802.15.4/ZigBee Wireless Sensor Network (WSN), is designed and implemented based on TSMC 0.18 μm RF CMOS process with low power dissipation and wide tuning range. The core circuit adopts complementary differential negative resistance LC oscillator structure and is...
A fast-lock all-digital register-controlled delay-locked loop (RCDLL) with wide-range duty cycle adjuster is presented. The architecture of the proposed fast-lock RCDLL uses the initial delay monitor without the delay line, which shares with the register controlled delay line for high accuracy of initial delay. Also, the duty cycle corrector of the DLL has achieved wide correction range to a small...
PRESENT, proposed by A. Bogdanov et al. in CHES 2007, is an ultra-lightweight symmetric cipher for extremely constrained environments such as RFID tags and sensor networks. In this article, a representative platform, 0.25 μm 1.8 V standard cell circuit is proposed to complement the PRESENT, the simulation-based ASIC experimental environment is built to acquire power data. According to the fact that...
In this paper, an applied mathematical method is proposed in which the effect of second order Intermodulation injection in elimination of the third order Intermodulation is examined and circuit parameters will be achieved with calculation to obtain the best IIP3 response of the circuit. The suggested mathematical technique is applied to a down converter Gilbert cell mixer in 2.4 GHz. This mixer is...
A high-speed current mode sense amplifier for Spin Torque Transfer Magnetic Random Access Memory (STT MRAM) is proposed. The sense amplifier is designed in a 0.18 μm CMOS technology, and 1.8 V supply voltage. The resistance values of high state is 2132 Ω, low state is 1215 Ω, and reference state is 1512 Ω, respectively. The proposed sense amplifier decreases the dropping rate of input bias. In particular,...
This paper presents a fast settling SRE (Slew Rate Enhancement) technique for operational amplifiers. An opamp using a constant-gm biasing together with the proposed SRE circuit is designed and it is shown that stable large and small signal characteristics can be achieved across the wide range of temperature. The opamp was designed and laid out in Jazz 0.18μm process using 1.8V supply voltage. The...
A high speed voltage comparator which can be used in high-speed Flash ADC is designed after considering the speed, offset voltage and other factors.The structure of the preamplifier and compare-latch circuit are analyzed .The high speed voltage comparator which consists of a preamplifier, a decision stage and an output buffer is based on SMIC 0.18μm CMOS process with 1.8 V power supply. The simulations...
This paper describes CMOS circuit design techniques for a limiting amplifier and received signal strength indicator (RSSI) circuits for the GPS receiver. The circuits in limiting amplifier and RSSI are all preudo differential to minimize the requirement of the supply voltage and be prepared against device mismatch. A folded diode load and folded cascade structure gain cell is introduced for each gain...
In this paper, a small area spread-spectrum clock generator (SSCG) with high EMI reduction for SATA-3.0 is presented. Conventional methods use inductor-capacitance (LC) tank to fulfill the high frequency requirement for SATA-3.0. However, the monolithic inductors always occupy a large area, and required precisely characteristic for different fabrication processes. This research propose a SSCG using...
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