The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
The aim of the work is to design and reduce the power consumption of low power 32 bits RISC core processor. The design is based on 5-stage pipelined DLX architecture. This paper proposes the design for the low power RISC processor. The DLX architecture with pipelined control in a RISC core consists of Fetch, Decode, Execute, Pipeline Control and Memory. The reduction in the power is achieved using...
This paper presents the low power compressor based Multiply-Accumulate (MAC) architecture for DSP applications. In VLSI, highly computed arithmetic cells including adders and multipliers are the most copiously used components. Efficient implementation of arithmetic logic units, floating point units and other dedicated functional components are utilized in most of the microprocessors and digital signal...
As the characteristic dimension shrinks to the nanometer scale, Multiplication unit in modern processors will become increasingly vulnerable in consuming much power and area. Existing logical optimization for placement and routing approaches in multiplication unit primarily focus on reducing the overhead and power consumption of FPGA's. However, our analysis shows that, the proposed method plays an...
Achieving low power consumption, size reduction, and space optimization are all challenges in resource-constrained wireless devices such as Wireless Sensor Network (WSN) nodes. For instance, WSN nodes use duty cycle to improve their power efficiency, and wake-up radio (WUR) is used as a control channel to wake the nodes up. With its highly flexible features, a field-programmable gate array (FPGA)...
Intrabody communications (IBC) is a novel communication technique which uses the human body itself as the signal propagation medium. This communication method is categorized as a physical layer of IEEE 802.15.6 or Wireless Body Area Network (WBAN) standard. It is significant to investigate the IBC systems to improve the transceiver design characteristics such as data rate and power consumption. In...
We demonstrate a power-efficient coherent interleaved frequency domain multiple access passive optical network (IFDMA-PON) uplink system. The digital signal processing circuits for coherent IFDMA-based quadrature phase-shift keying (PSK) are implemented on 40-nm field programmable gate arrays. By employing polar-coordinate transformed mapping of the PSK signal, the power consumption of the optical...
In recent years, with the rapid development of the Internet, ever increasing traffic and link-bandwidths presented serious challenges for computer network-related research such as high-speed algorithm and development of high-performance network equipment. Of course, increasing complication in hardware, firewall filtering and Encryption technology, makes programmability getting more and more attention...
Due to the ever increased energy consumption, large research effort has devoted to the energy efficiency area. In this paper, a frequency scalable publish-subscribe filter forwarding node has been proposed and implemented for addressing this challenge. The frequency scaling filter can operate on three different frequencies, which adapts its capacity and power on different network throughput. Our work...
Content Addressable Memories (CAMs) have been widely used to implement various high speed search functions in network devices such as routers and servers. In these devices, the role of CAM is to classify, drop or forward internet packets (i.e., packet classification). However, CAM suffers from several shortcomings such as high power consumption and low integration density. In addition, CAM is not...
Using passwords for user authentication is still the most common method for many internet services and attacks on the password databases pose a severe threat. To reduce this risk, servers store password hashes, which were generated using special password-hashing functions, to slow down guessing attacks. The most frequently used functions of this type are PBKDF2, bcrypt and scrypt. In this paper, we...
Heterogeneous computing is gaining attention from both industry and academia nowadays. One driving factor for heterogeneous computing is the power efficiency. GPU and FPGA have been reported to achieve much higher power efficiency over CPU on many applications. Comparisons between GPU and FPGA show different characteristics of GPU and FPGA in accelerated computing. Some tasks run better on GPU, some...
In this paper, we discuss a number of issues emerged from our twenty-year long experience in applying the Residue Number System (RNS) to DSP systems. In early days, RNS was mainly used to reach the maximum performance in speed. Today, RNS is also used to obtain power-efficient (tradeoffs speed-power) and reliable systems (redundant RNS). Advances in microelectronics and CAD tools play an important...
This paper presents a hardware implementation of morphological operations based on dynamic and partial reconfiguration (DPR) technique. This technique allows reconfiguring a part of the FPGA area with different functionalities at runtime. It is a promising solution toincrease performance in the system. Our design allows todesigner to choose the adequate morphological operation (erosion or dilation)...
This paper, deals with Latch Free Clock Gating technique for reduction of clock power and total power consumption in Low Power Arithmetic and Logic Unit and we have analysed power reduction on different FPGA devices. Without latch free clock gating technique in Low Power Arithmetic and Logic Unit the Contribution of Clock power was 39mW in Virtex-6 FPGA, 14mW in Virtex-5 FPGA, 24mW in Virtex-4 FPGA,...
In this paper, we have proposed the design of energy efficient and high frequency frame buffer on 40 nm FPGA. The operational frequency of buffer is kept quite high of 1THz and it has been recorded that we need to optimize power considerations in order to reduce the power consumption. The values are recorded on LVCMOS and LVDCI. For LVCMOS, we recorded that average power consumed is 88W and for LVDCI...
Stub Series Terminated Logic (SSTL) is an Input/output standard. It is used to match the impedance of line, port and device of our design under consideration. Therefore, selection of energy efficient SSTL I/O standard among available different class of SSTL logic family in FPGA, plays a vital role to achieve energy efficiency in design under test (DUT). Here, DUT is ROM. ROM is an integral part of...
Multiply and Accumulate is the main component of the DSP System, which is the major block for power consumption and decides the speed of the overall system due to its complex operation. Hence in most of the DSPs, it lies in the critical path. In this work, Low power MAC architecture has been proposed by examining the critical paths and the hardware complexities. Proposed is a generic architecture...
The main aim of this work is to study and show power reduction by using clock gating techniques with pulse enable concept. In this two 8 bit input data and a MUX 4:1 for selection of instruction which is a combination of logic and arithmetic operation's and total of 11 instruction are performed in the proposed design. This technique is applied on the D Flip-Flop based gated clock ALU & negative...
Dynamic energy pricing is a promising technique in the Smart Grid that incentivizes energy consumers to consume electricity more prudently in order to minimize their electric bills meanwhile satisfying their energy requirements. This has become a particularly interesting problem with the introduction of residential photovoltaic (PV) power generation facilities. This paper addresses the problem of...
In print image, a watermark is an identifiable pattern which when viewed by reflected light seems to have different shades of lightness. In digital image, a watermark is a pattern, which is embedded in image to ensure the security and quality of an image. In this work, our main concern is design of energy efficient Watermark Generator (WMG) for video frame in order to gain extended life of the battery...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.