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An analog baseband chain for a Synthetic Aperture Radar (SAR) receiver implemented in a 130nm CMOS technology is presented in this paper. Occupying 0.23mm2 of silicon area, the baseband chain consists of a three-stage Variable Gain Amplifier (VGA), a 5th-order gm-C Low Pass Filter (LPF) and an Output Buffer (OBUF). The gain of the chain can be controlled by tuning the control voltages of the VGA and...
This paper presents an analysis on energy dissipation of a digital half band filters operated in the the sub-threshold (sub-VT ) region with throughput constraints. The degradation of speed in the sub-VT domain is counteracted by unfolding the architectures. A filter is implemented in a basic 12-bit and its various unfolded structures. The designs are synthesized in a 65 nm low-leakage high-threshold...
This paper presents the architecture and the corresponding simulation results for a digitally interfaced ultra-low power extended Hamming decoder implemented in analog integrated circuitry. ST's 65nm low power CMOS design library was used to simulate the complete decoder including a serial input digital interface, an analog decoding core and a serial output digital interface. The simulated bit error...
Exclusive-OR (XOR) gate is one of the critical components in many applications such as cryptography. In this paper, we present an efficient multi-input XOR circuit design based on pass-transistor logic (PTL). A synthesis algorithm is developed to efficiently generate the PTL-based multi-input XOR circuits. Both pre-layout and post-layout simulation results show that our proposed multi-input XOR design...
A low-power complementary metal oxide semiconductor(CMOS) operational amplifier(op-amp) is proposed for real-time signal processing system of microsensor. This proposed implementation was based on traditional folded cascode op-amp architecture with positive channel metal oxide semiconductor (PMOS) differential input transistors, which is the best choice for lower-power applications. Simultaneously...
A key problem of attitude measurement of small-multi-target with high speed is how to decide the optimum of the CMOS stations. A multi-CMOS station mode is designed in this paper, multiple CMOS videos were placed on two parallel sides in measurement system, every two CMOS form an intersection viewing field, multiple viewing field join to cover shooting range, which can augment Effective Viewing Field...
As is known to all, luminance and luminance distribution are both important factors influencing people's impression of the luminous environment. The traditional measuring devices are hard to meet the demand of lighting practice. A CCD-based luminance meter could evaluate the luminance of several small portions of a surface (“point” luminance). Although some manufactures have already produced reliable...
A low-power complementary metal oxide semiconductor (CMOS) bandgap current reference is proposed under the 1.8V supply voltage. The temperature compensation current generator was used in order to obtain an accurate 5μA current with lower temperature coefficient. Sub-threshold technology and advanced startup circuit were adopted to decrease the circuit power consumption. The current reference has been...
A 5V, 0.6μm CMOS phase locked loop (PLL) is presented. The circuit design of the PLL, which consists of a phase-frequency-detector (PFD), charge-pump (CPP), bias-generator (BG), voltage controlled oscillator (VCO) and differential to single converter (DSC), is introduced and the simulation results are given. The details of design theory and calculation are also described. The PLL is integrated in...
While analog part of the integrated circuit covers 10% of its area its design takes 90% of the time needed to design the whole circuit. Therefore analog synthesis is very hot topic at present. It can save enormous part of the design time. This paper presents work on novel analog synthesis tool capable of choosing circuit architecture and to size its devices by optimization to meet the design specification...
Voltage references are essential components of analog VLSI circuits. A reference source is expected to remain constant against temperature and supply voltage fluctuations. First order bandgap voltage references show variation in terms of 'mV against temperature, which may not be adequate for some high precision applications. Curvature corrected bandgap reference(BGR) is an attempt to improve stability...
In earlier, Fault Analysis (FA) has been exploited for several aspects of analog and digital testing. These include, test development, Design for Test (DFT) schemes qualification, and fault grading. Higher quality fault analysis will reduce the number of defective chips that slip past the tests and end up in customer's systems. This is commonly referred to as defective parts per million (DPM) that...
This paper presents an extended CAD tool compatible with decananometric technologies for sizing OTA architectures. This is based on an extension of the gm/I methodology which uses, as inputs, parameters directly extracted from foundry models and can hence be easily ported to different technologies. This tool was developed in order to fasten and automate design for each OTA architecture. From fixed...
In this paper, a new compact, low power and low voltage structure for CMOS analog multiplier is proposed. All of them are implemented using a compact circuit. The circuit is designed and analyzed in 0.18μm CMOS process model. Simulation results for the circuit with a 1.2V single supply show that it consumes only 25μw quiescent power with 2GHz bandwidth and 1.5% THD.
In this paper, a new low voltage topology for analog multiplier is presented. The circuit can be used with single low-power supply. The complete circuit has only twelve transistors; therefore, it satisfies the need for compact sub-circuit in analog VLSI systems. The mathematical discussion on the power consumption, total harmonic distortion and other features of the circuit and also simulation results...
The design plan and HSPICE measurement of a high acquisition speed for a sample of 8-bit CMOS differential successive approximation register (SAR) Analog-to-digital converter (ADC) are presented. The operation of the conventional main switch-capacitor array is divided into two switch-capacitor arrays. Such that, one switched-capacitor array is used to define the four most-significant bits, while the...
Low dropout voltage regulators (LDO) use a large external capacitor, in the range of few micro-farads. These external capacitors occupy valuable board space, increase the IC pin count and prohibit System-On-Chip (SoC) solutions. The large external capacitor is replaced with a reasonable InF internal capacitor. The capacitor-less LDO is designed for an output voltage of 1.4V for a given supply voltage...
A design of a low dropout voltage regulator (LDO) with fast settling response is being reported. This circuit is stable for full load current range from 0 to 150mA. A current boost circuit is being used to improve the transient response. There was an overshoot of mere 10.51mV and settling time achieved was 43.8ns. The PSRR achieved was -84.464dB upto 8.895kHz, and more than -70db till 136.218MHz....
This paper describes a graphical method for the optimization of Quadrature Voltage Controlled Oscillators (QVCOs) based on the coupling of two LC-tank VCO. A three-dimensional phase noise analysis diagram and graphical optimization approach is presented, to optimize QVCO phase noise while satisfying design constraints such as power dissipation, tank amplitude, tuning range and start up condition....
This brief proposes a novel multi-objective heuristic. It is a transformation of a mono-objective heuristic into a multi-objective one by addition of an archive and some non dominance computing routines. Performances of the proposed heuristic are demonstrated thru test functions. An application to the optimal sizing of a class AB second generation CMOS current conveyor is presented. Comparison with...
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