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The low power successive approximation register (SAR) analog to digital converter (ADC), which implements the two-step switching, is designed and simulated in 65 nm CMOS of ST Microelectronics. The two-step switching allows to benefit from the more energy-efficient switching because of the use of three voltage levels without any requirements for stability and accuracy of the third voltage level. Post-layout...
The paper suggests very fast electronic solutions for priority buffers that take data from many potential sources, accumulate them in a register, and output the most priority item in run time in such a way that as soon as a new value arrives it is included in the set with all previously received and untreated items and properly handled. It is shown that such circuits are required for real time embedded...
The paper discusses total ionizing dose degradation of 8-transistor CMOS-sensor. Nonuniform degradation of different columns was observed. A way to eliminate radiation induced degradation and thus enhance the hardness level is proposed.
This paper presents the system that allows SEFI modelling by means of injecting upsets in different microcontroller memory blocks, carrying out its functional control and detect the moment when SEFI occurs. Test setup was developed on the basis of National Instruments PXI modular equipment and LabVIEW software. Developed fault injection system was tested on PIC17 microcontroller. The comparison between...
Post Silicon Validation is critical step in order to deliver quality microcontroller chips to customers but is increasingly becoming complex and time consuming process as the design size is increasing. Due to increased number & diversity of design intellectual property, microcontroller post silicon validation has moved towards customized validation concept and hardware setup for individual design...
Designing and optimizing computer systems require deep understanding of the underlying system. Historically many important observations that led to the development of essential hardware and software optimizations were driven by empirical studies of program behavior. In this paper we report an interesting property of dynamic program execution by viewing it as a changing (or social) network. In a program...
A novel architecture of Integer Motion Estimation (IME) for High Efficiency Video Coding (HEVC) processing 8K video is presented in this paper. This architecture achieves 8K (7680×4320) video in real time at 45 fps (frames per second) with frequency of 96.4 MHz and latency of as low as 260 clock cycles. The proposed design has been implemented by Xilinx ISE 13.1 using Virtex-7 28nm technology.
The increasing use of digital signal processors (DSPs) in wireless communications and signal processing necessitates the optimization of compilers to support special hardware features. In this paper, we propose a compiler transformation method for zero overhead loop (ZOL). It supports very long instruction word (VLIW), internal branches and the loops whose iterative times are known at runtime and...
In the system on chip design process, functional validation is regarded as one of the main challenges. One sub problem in functional validation is proving the unsatisfiability of certain properties such as the reachability of some assertions or code blocks. In this work, we present a induction-based bounded model checking technique using a Satisfiability Modulo Theories (SMT) solver for proving the...
Over the past few years we have articulated theory that describes ‘encrypted computing’, in which data remains in encrypted form while being worked on inside a processor, by virtue of a modified arithmetic. The last two years have seen research and development on a standards-compliant processor that shows that near-conventional speeds are attainable via this approach. Benchmark performance with the...
The trends of transistor size and system complexity scaling continue. As a result, soft errors in the system, including the processor core, are predicted to become one of the major reliability challenges. A fraction of soft errors at the device level could become an unmasked error visible to the user. Unmasked soft errors may manifest as a detectable error, which could be recoverable (DRE) or unrecoverable...
In converters possessing multiple distributed controllers the synchronization of and the communication between the various controllers are important topics requiring careful consideration. The controllers should be able to transmit data and commands to each other so that different control modes can be selected, reference values updated, parameters shared and so forth. Synchronization is important...
Traditional processor design approaches using CISC and RISC philosophies suffer from low performance. One of alternative approaches to improve system performance is instruction level parallelism (ILP). Among the processor architectures supporting ILP, very long instruction word (VLIW) processors offer some advantages such as low power consumption and hardware complexity. In this paper, we introduce...
In this paper, we report our experiences in designing, deploying, and making continuous improvements of a Privacy-Aware Compliance Tracking System (PACTS) at a skilled nursing facility. The purpose of PACTS is to help state tested nursing assistants (STNAs) get into the habit of using proper body mechanics when performing bedside cares. The system has been deployed in six resident rooms and seven...
In recent times, there has been much interest in quantum enhancements of machine learning, specifically in the context of data mining and analysis. Reinforcement learning, an interactive form of learning, is, in turn, vital in artificial intelligence-type applications. Also in this case, quantum mechanics was shown to be useful, in certain instances. Here, we elucidate these results, and show that...
Principle of graphic collection system based on PCI9054 and DSP was introduced in order to collect information outside rapidly and instantly in the paper. The telecommunication of collection card and host computer by PCI9054 interface chip was introduced, the logical programmed module was introduced simplified the design of digital logical circuit and implemented the transform of graphics format,...
In the process of multi axis machine tool, sometimes it is necessary to switch between the rotating spindle and the rotary feed shaft. In order to satisfy the request mentioned above, this article makes a brief introduction to the upper software and analyzes the control principle of spindle by using PMAC, combined with that, a method to deliver the automatic switching function between spindle mode...
This paper proposes a power-stable code based DPA resistant technique for AES encryption circuit. The power-stable code is adopted to stabilize the leaked power consumption of key logic circuit. In this paper, the circuits of Addroundkey is designed with the proposed technique for standard AES algorithm. The real-time power consumption of designed circuits are recorded from oscilloscope. DPA attack...
This paper presents an addition and multiplication computation cell using pulse train time amplifier (TA) and time register (TR), which could be easily extend to large-scale computation. The proposed pulse train TA exploits a delay cell ring to realize large input range. In TR a gated delay line with MOS capacitor is adopted to achieve both large number computation and high resolution. Finally, a...
This paper presents a Soft-Edge Error-Detecting Flip-Flop (SEED FF), which can be used in Ultra-Low-Voltage (ULV) digital circuits to address timing variation problems with a lower timing error correction rate. The master latch's clock edge of a timing error detecting flip-flop is delayed so that it has not only the timing error detection capability but also a narrow transparency window. HSPICE simulations...
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