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We report the first experimental evidence of discrete threshold-voltage transients on high-density NAND Flash arrays during post-cycling data retention. Proper choice of experimental conditions eliminates the impact of averaging effects and disturbs on the transients, enabling clear detection of single charge emission events from/to the tunnel oxide of sub-30nm NAND Flash cells. A stochastic model...
In this work we present a detailed investigation of TANOS memory reliability, focusing on issues raised by Al2O3 trapping/detrapping and leakage. These effects are investigated as a function of alumina thickness, electric field and temperature, comparing experimental and modeling results for trap parameters extraction. For TANOS devices, Al2O3 charge storage modifies program and erase saturation level...
Buffer traps can induce ldquofalserdquo surface-trap signatures in AlGaN-GaN HEMTs, namely the same type of current-mode DLTS peaks and pulse responses that are generally attributed to surface traps. Device simulations are adopted to clarify the underlying physics. Being aware of the above phenomenon is important for both reliability testing and device optimization, as it can lead to erroneous identification...
Reliabilities of high-k stacked gate dielectrics are discussed from the viewpoint of the impact of initial traps in high-k layer. TDDB reliability can be explained by the generated subordinate carrier injection (GSCI) model. While initial traps increase the leakage current, they do not degrade the TDDB reliability. In contrast, the BTI reliability is strongly degraded by initial traps.
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