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With continuous shrinking in the size of deep sub-micron in this million transistor era, the interconnection of these hundreds and thousands of cores on a single chip is still constraint. Providing an efficient communication among these cores is a major challenge in the on-chip domain. Although hierarchical architecture has addressed most of the issues of the traditional approaches like point-to-point...
This paper explores the possibility of building a flexible Low Density Parity Check (LDPC) decoder using a network on chip communication infrastructure. Even if this idea is not completely new, previously published works suffered from an excessive area occupation and their practical impact has been very limited. In the following we analyze two possible NOCs specifically designed for the LDPC case...
NoC is a potent solution to address design complexity and productivity problems whose its key component is the interconnect architecture which directly affects both cost and performance parameters. The purpose of this paper is to present the basic ideas behind the development of our new hierarchical network-on-chip (NoC) architecture, called ldquoNormardquo that its most distinguished characteristic...
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