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In this paper a BISR architecture for embedded memories is presented. The proposed scheme utilises a multiple bank cache-like memory for repairs. Statistical analysis is used for minimisation of the total resources required to achieve a very high fault coverage. Simulation results show that the proposed BISR scheme is characterised by high efficiency and low area overhead, even for high defect densities...
In this paper, the characteristics of the basic current mirror and the continuous-time current-mode current mirror integrator are analyzed. Using the two unlossy loop integrators and the basic current mirrors, the biquad circuit block is implemented. The signal flow graph (SFG) and the improved leap-frog (ILF) structure are simple to implement the six-order band pass filters. Exploring PSPICE9.1 simulation...
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