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This paper reports about the development and application of a new test chip for stress analysis in microelectronic packaging processes and reliability tests. Special focus will be on transfer molding with epoxy molding compound (EMC). The CMOS based stress sensor is able to measure in-plane normal stress and shear stress on the chip surfaces with an absolute stress resolution of plusmn 3 MPa. By the...
This paper reviews recent experimental confirmations that the intrinsic radiation robustness of commercial CMOS technologies naturally improves with the down-scaling. When additionally using innovative design techniques, it becomes now possible to assure that performance and radiation-hardness are both met. An illustration is given with an original nano-power and radiation-hardened 8 Mb SRAM designed...
Polarities of plasma charging damage in n- and p-channel MOSFETs with Hf-based high-k gate stack (HfAlOx/SiO2) were studied for two different plasma sources (Ar-and Cl-based gas mixtures), and found to depend on plasma conditions, in contrast to those with conventional SiO2. For Ar-plasma, which was confirmed to induce a larger charging damage, both n- and p-ch MOSFETs with high-k gate stacks suffer...
3D contactless technology based on capacitive coupling represents a promising solution for high-speed and low power signaling in vertically integrated chips. AC coupled interconnects do not suffer from mechanical stress, and the parasitic load is much reduced when compared to standard DC solutions, such as wire bonding and micro bumps. Communication system based on wireless interconnection scheme...
This work reports real-time soft-error rate (SER) testing of semiconductor static memories in both altitude and underground environments to separate the component of the SER induced by the cosmic rays (i.e. primarily by atmospheric neutrons) from that caused by on-chip radioactive impurities (alpha-particle emitters). Two European dedicated sites were used to perform long-term real-time measurements...
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