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With the rapid development of deep submicron (DSM) VLSI circuit design, many issues such as time closure and power consumption are making the physical design more and more challenging. This paper proposes a method aiding in low clock skew which is applicable to the clock tree synthesis (CTS) design flow. The method works by breaking up the original clock root into several pseudo clock sources at the...
In recent years, as SoC design research is actively conducted, a large number of IPs are included in one system through network on chip. The real effort and time in using NoC is spent in developing network interfaces (NI) for connecting cores to the NoC. The area and power of NIs should be small and its latency must be kept as low as possible. To reduce power dissipation NIs, we suppose to employ...
Networks-on-Chip (NoC) have emerged as a replacement for traditional shared-bus designs for on-chip communications. As with all current VLSI design, however, reducing power consumption in NoCs is a critical challenge. One approach to reduce power is to dynamically scale the voltage and frequency of each network node or groups of nodes (DVFS). Another approach to reduce power consumption is to replace...
State of the art VLSI systems are characterised by their small, deca-nano feature size. In order to accommodate the complexity and scalability, a new design paradigm, system on chip (SoC) has been introduced. Performance and power of giga-scale SoC is ever more communication-dominated. However typical SoC communication infrastructure is based in standard buses and protocols which are difficult to...
The Niagara2 CMT system-on-chip incorporates many design-for-test features to achieve high test coverage for both arrays and logic. All the arrays are tested using memory built-in-self-test. This is supplemented with scan-based testing. Logic is tested with standard ATPG for slow-speed defects and extensive use of transition test, along with logic built-in-self-test for the SPARC cores, for at-speed...
3D contactless technology based on capacitive coupling represents a promising solution for high-speed and low power signaling in vertically integrated chips. AC coupled interconnects do not suffer from mechanical stress, and the parasitic load is much reduced when compared to standard DC solutions, such as wire bonding and micro bumps. Communication system based on wireless interconnection scheme...
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