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Evaluating the performance of Multiple Target Tracking algorithms is a crucial requirement for the design and validation of different applications. Most of the available evaluation metrics require knowledge about the true state of the estimated situation. However, in most practical applications, such reference data are not available. Thus, a system of performance evaluation metrics which do not require...
This paper discusses the design of a 60 GHz low noise amplifier (LNA) using a standard low power SOI CMOS process from ST Microelectronics. First, we outline the technology as well as the mm-wave design challenges. Using recent work on coplanar waveguide (CPW) modeling, we describe how it's possible to use parametric, 3D electromagnetic simulation to complete or replace analytical models of on-chip...
A high bandwidth critical path monitor (1 sample/ cycle at 4-5 GHz) capable of providing real-time timing margin information to a variable voltage/frequency scaling control loop is described. The critical path monitor tracks the critical path delay to within 1 FO2 inverter delay with a standard deviation less than 3 FO2 delays over process, voltage, temperature, and workload. The CPM is sensitive...
A circuit for on-chip measurement of long-term jitter, period jitter, and clock skew, is demonstrated. The circuit uses a single latch and a voltage-controlled delay element, and is evaluated in a stand-alone pad frame. Excellent reproduction of jitter measured by oscilloscope is shown. Measured jitter resolution is 1 ps or better. The circuit is also incorporated into a 2 GHz clock distribution network...
In the paper we describe a method to extract the topography of an impressed current for our bounded electrical impedance tomography (bEIT) studies. The frequency of the impressed current is low (up to a few hundred Hz), and is buried in background EEG and other noise. For the development of the extraction method, special consideration is given to maximize the signal-to-noise ratio. The standard lock-in...
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