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This paper presents design of a new stable 14T full power efficient adder circuit. The proposed circuit is designed based on Pass Transistor Logic (PTL) network using NMOS transistor only. The proposed circuit is simulated at layout level using Microwind EDA tools for 45nm technology in terms of power and voltage level at the sum and carry nodes. The proposed circuit performance is compared with a...
This study attempts to make use of traffic behaviour on the aggregate level to estimate congestion on urban arterial and sub-arterial roads of a city exhibiting heterogeneous traffic conditions by breaking the route into independent segments and approximating the traffic flow behaviour of the segments. The expected travel time in making a trip is modelled against sectional traffic characteristics...
Through Silicon Vias (TSVs) are crucial elements for the reliable operation and the yield of three dimensional integrated circuits (3D ICs). Resistive open defects are a serious concern in TSV structures. In this paper, a post-bond, parallel testing technique is proposed for the detection and location of resistive open defects in TSVs, which is based on easily synthesizable all digital testing circuitry...
The presence of metallic tubes and CNT diameter variation impacts delay of critical paths in CNFET circuits. Consequently, variations in critical path delays impact functional yield. We propose to predict circuit performance and yield using a statistical approach, rather than the worst-case method, to the critical path delay evaluation. We consider the CNT diameter variation and the number of tubes...
With the extensive application of train communication network, more and more data transmission delay and interference packet loss occurred, which causes great threat to train safety and stable running. It is necessary to study the transmission and distribution characteristics of the network control delay of high-speed EMUs, and take effective measures to reduce the impact of time delay on train control...
The main requirement of Very Large Scale Integration (VLSI) circuit is to be fast and low energy consumption. So, the analysis is done by optimizing the delay, which results in fast processing and low average energy consumed. A 3 transistor XNOR gate is proposed. The proposed XNOR gate is designed using CADENCE EDA tool and simulated using the SPECTRE VIRTUOSO at 90 nm technology. The results from...
In recent trends of VLSI technology the reversible logic has became the major area of research in optimization of area, power and speed constraints. The reversible logic has equal number of inputs and outputs. In wireless communications Viterbi algorithm is employed to have minimal number of communication channels. The Viterbi decoder design at 65nm technology using reversible logic has made an attempt...
FinFETs are the devices which replaced bulk MOSFETS because of its surpassing quality of minimizing leakage power and reducing short channel effects occurring in MOSFETS due to decrease in channel length. In this paper a comparative analysis of proposed Voltage Mode Sense Amplifier (VMSA) is performed using FinFET and CMOS at different technology node. Simulation is carried out using H-spice tool...
Arithmetic and Logic Unit represent the core of all microprocessors. It performs arithmetic and logical operations. ALU is getting more complex and smaller to make more efficient circuits. This paper describes simple ALU but contains the essentials functions. It is a reconfigurable ALU based on double gate carbon nanotube field effect transistors (DG-CNTFETs). The proposed ALU is designed for one...
A 3 MHz, 48W Boost converter with high speed and high accuracy Peak Current Control Unit (PCCU) is presented. The Boost controller IC adopts a novel PCCU consisting of a fully differential open-loop operational transconductance amplifier (OTA) and a trans-impedance amplifier (TIA), which can minimize the delay and error of the whole control loop. In the PCCU, the compensated output of error amplifier...
Passive optical network (PON) has become the vital technology for the next generation access networks. The advancement of optical technology extends the span of the PON from 20 to 100 km. Such an extended PON is known as Long-Reach PON (LR-PON). But the data transmission in the existing LR-PONs suffer from longer propagation delays between the optical line terminal (OLT) and optical network units...
Adders are one of most essential components of the digital circuits that are designed for different DSP applications. The important aspects considered for designing any digital circuit design are delay, power and Power Delay Product (PDP). In this paper, 32 bit carry bypass adders (CBA) which have superior performance with respect to these parameters are presented. The CBA's are implemented using...
We propose a traffic prediction algorithm that reduces the packets delay in Ethernet Passive Optical Networks (EPONs). The algorithm relies on Multi-Point Control Protocol (MPCP) message and traffic monitoring at the Optical Network Units (ONUs) and utilizes the monitoring information to predict the accumulated burst size using higher order least-mean-square polynomial approximations. The simulation...
For 7 series Xilinx FPGAs, this paper shows that it is risky to believe that so fundamental operation as data delay must be always implemented without wasting chip area, even when design tools are not especially guided by a developer. Against this background, two solutions are presented that allow for minimizing the area occupied by flip-flops used to delay data that comes from outside the slices...
In industrial automation fields, seamless connection of the capabilities of smart wireless devices to a high-bandwidth and deterministic real-time Ethernet-based industrial backbone has emerged as an important research focus. This study describes a method for integration of WirelessHART networks into the Ethernet Powerlink backbone. A Linux-based open Powerlink-WirelessHART gateway (PW-GW) solution...
Approximate or inexact computing has recently attracted considerable attention due to its potential advantages with respect to high performance and low power consumption. This paper presents the design of an approximate multiplier; this approximate multiplier consists of an approximate Booth encoder, an approximate 4-2 compressor and an approximate tree structure. The approximate design is implemented...
Now a days, low power Very Large Scale Integration (VLSI) circuit plays an important role in designing efficient energy saving electronic systems for high speed performance. In VLSI, low power dissipation is the main criterion in many electronic devices out of speed, area, etc., like mobile phones, laptops, high speed work stations etc., Due to the integration of many components on the VLSI circuit...
With the increasing complexity of electronic circuits and to meet the demand of high performance, the design and optimization of electronic circuits need to be automated with high degree of reliability and accuracy. In order to optimize hardware requirements of digital combinational circuits, evolutionary and innovative techniques need to be enforced at various levels such as at gate level and device...
This present paper, a 3 transistor XNOR gate is proposed. The proposed XNOR gate is designed using CADENCE EDA tool and simulated using the SPECTRE VIRTUOSO at 180 nm technology. The proposed results are compared with the previous existing designs in terms of power and delay. It is observed that the power consumption is reduced by 65.19 % for three transistor XNOR gate and 48.11% for eight transistor...
Internet of Things (IoT) is considered to be the next revolution in the field of wireless communications. This concept involves mapping of physical world to virtual (cyber) world. It is achieved by interconnecting devices having sensing capabilities using unique addressing scheme and passing their collective information to the IoT cloud. However at present, these devices belonging to different technologies...
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