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This paper presents a new NoC Interface (NI) targeted for improving the performance of the Micronmesh Multiprocessor System-on-Chip (MPSoC). The previous version of the NI called Micronswitch Interface (MSI) can zero-copy messages as it sends and receives them. It offloads also some functionalities of the communication protocol from software (SW) to hardware (HW), but interrupt processing produces...
Multi-parallel architecture for MD5 (Message-Digest Algorithm 5) implemented on FPGA (Field-Programmable Gate Array) is presented in this paper. To accelerate the speed, a general architecture for Host Computer and FPGAs is proposed. The MD5 implementation is presented. Besides the internal parallelization of MD5 modules, FPGAs can be easily duplicated and connected to Ethernet LAN. The design was...
Advanced Encryption Standard (AES) and state of art technology FPGAs (Field Programmable Gate Arrays) can be used together to mitigate the potential threats of interception of Satellite data and unauthorized access to the Satellite System. This paper discusses the implementation and verification of AES algorithm on Virtex 4 FPGA and its usage in the protection of Remote Sensing Satellite Data. The...
In this paper, a very high-throughput and area efficient hardware decoder of the binary (23, 12, 7) Golay code is presented. The key feature of this proposed algorithm is fast determination of the error positions through the analysis on the weight of syndromes without large operations of finite fields. Comparing with the algorithm using one syndrome, the proposed algorithm is more suitable for the...
Multiprocessor system-on-chip design (MPSoC) is becoming a regular feature of the embedded systems. Shared-bus systems hold many advantages, but they do not scale. Network on chip (NoC) offers a promising solution to the scalability problem by enhancing the topology design. However, standard NoCs are only scalable within a chip. To be able to build infinitely scalable structures, a method to enhance...
Multi-cipher and multi-mode cryptosystems are widely used for hardware acceleration in modern security protocols. In a session of communication, these protocols can only use an algorithm along with its operation mode. The switching of cipher algorithms and operation modes can occur between sessions of communication. This paper introduces a multi-cipher cryptosystem (MCC) which enables a cryptosystem...
This paper proposes a novel frame memory compression algorithm, called pixel-parallel SPIHT (PPS) that processes image data in parallel to increase the encoding throughput. The throughput of a PPS coder is an average of 4.48 bits per cycle which is 48.7 times larger than that of No List SPIHT.
The VLSI implementation of maximum likelihood (ML) detection for higher order multiple input multiple output (MIMO) systems continues to be a major challenge. Battery driven handheld devices impose strict area and power constraints while demanding guaranteed performance over a wide range of operating conditions. This paper presents a modified, low complexity K-best detector for a 4??4, 64 QAM MIMO...
This paper presents the design of an ultra high speed crypto-processor for next generation IT security. It addresses the next generation IT security requirements: the resistance against all attacks and high speed with low latency. The proposed processor is capable of generating cryptographically secured information at a rate of multi-ten Gbps. The performance of the processor is compared with that...
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