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A synthesis-based bandwidth enhancement technique for CMOS amplifiers/buffers is presented. It achieves bandwidth-enhancement ratio (BWER) of 4.84, close to a proven theoretical upper limit of 4.93 for passive network with balanced capacitive loads. By employing a step-by-step design methodology, the proposed technique can be applied to any load condition, which is characterized by the ratio between...
This paper presents a low power, high gain, fully differential ultra-wide bandwidth operational amplifier with wide dynamic range. The design uses two-stage gain, high swing common-mode feedback, `doublet-free' pole-zero cancellation and gm-boosting techniques to increase the unity gain frequency to about 1.5 times that of the widely used class-A common source output stage at similar power consumption...
A technique for power-bandwidth scaling of a current feedback amplifier (CFA) is presented. By employing current gain, instead of the feedback resistance, to alter the closed-loop bandwidth of the CFA, the proposed approach is shown to provide 30% quiescent power savings for a bandwidth variation of 10MHz to 100MHz. Parasitic extracted simulations are performed in a 0.18μm CMOS process with a power...
This paper presents a CMOS fully differential folded cascode that operates at high frequency. Theoretical study on this amplifier is first presented and analyzed. The crucial parameters that may have influences on the trade-off for the design of this amplifier are also presented. Simulation results showing the characteristics of this amplifier are discussed. Using technology CMOS 0.18 μm with power...
An X-band high efficiency power amplifier with the highest PAE is presented in this letter. The single-stage power amplifier is implemented in TSMC standard bulk 0.18-μm 1P6M CMOS technology. In order to obtain wide bandwidth at PAE and output power, broadband output and input matching network are adopted in the design. From the measurements, the power amplifier obtained the best PAE of 25.8% and...
A 2-6 GHz WiMAX low noise amplifier (LNA) is designed and implemented in 0.18-??m CMOS process. This low noise amplifier utilizes a current-reused technique, and a high-pass input matching network. The LNA presents a maximum power gain of 18.4 dB at 2 GHz. The minimum noise figure (NF) is 2.1dB. S11 is less than -16 dB. The total power consumption is 17.4 mW under a 1.8 V power supply. The chip size...
A new ultra low-power CMOS Electromyograph (EMG) amplifier is presented in this paper. It is based on the application of a novel capacitive load reduction circuit technique to the capacitive-reset switched-capacitor circuit architecture. This is achieved by adding a capacitor in series with the capacitive load of the amplifier so as to reduce the total effective load capacitance being seen by the...
A new approach for diagnostic analysis of bandwidth mismatch in time-interleaved systems based on gradient search method is proposed. The algorithm is adaptive to slow changes in mismatch errors and does not require any information about the input signal. Additionally, the information acquired can be re-used to supplement the circuit calibration. The proposed method is evaluated on a prototype sample-and-hold...
A linear-in-dB CMOS variable gain amplifier (VGA) targeting a low power read channel front-end is presented. Biased with a less than 2 mA current, this VGA provides 6-18 dB amplification and more than 700 MHz 3-dB bandwidth with less than -45 dB THD in 0.18-mum CMOS. In addition, the 6-18 dB gain is continuously tunable by adjusting the bias current. With such a performance trade-off, it is well suited...
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