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Photonic systems are being increasingly designed for multi-functional, distributed avionic platforms to satisfy the next-generation military needs [1]. This approach requires establishing high-capacity, Free-Space Optical (FSO) communication networks that connect a variety of mobile and aerial platforms in an ad-hoc fashion [2]. Traditional design methodology, that addresses a specific scenario with...
In this paper, an advanced joint jammer with deceptive jamming and blanket jamming is proposed for countering linear frequency modulated (LFM) radar. Multiple preceded and hysteretic false targets are produced by convolution operation and the blanket jamming is obtained by modulating the intercepted hostile radar signal according to pseudo-random sequences. The jamming algorithm is implemented on...
A 10–60 Gb/s wireline transmitter with a 4-tap multiple-multiplexer (MUX) based feed-forward equalization (FFE) is presented. It adopted a novel 4:1 MUX to increase the bandwidth of the final seiralizing stage. Simulation result shows that the proposed 4:1 MUX operates over a wide range of data rate between 10 and 60 Gb/s. Designed in 65 nm CMOS technology, the transmitter exhibits a low jitter of...
We demonstrate an electro-optical switching based demultiplexing scheme for high-speed photonic analog-to-digital converter system. In a 20 GHz actively mode locked laser based photonic analog-to-digital converter system, a Mach-Zehnder modulator is used as the electro-optical switching to demultiplex the 20 GS/s sampled series into two channels at the speed of 10 GS/s, which are then digitized at...
FPGA-based neural-networks typically leave performance on the table because the DSP resources run at less than a third of the peak clock rate. This paper presents a processing array architected to consistently achieve timing closure at 100% of the peak DSP clock rate with standard FPGA tools. In the HDL design environment, our processing array operates at the peak DSP clock rates on Xilinx UltraScale...
This work studies a digital transmission system by fiber optic. We give special relevance to the synchronism block. The fiber is a transmission medium with large bandwidth and low attenuation. These characteristics allow high speed and long distances. The transmission, instead asynchronous, it is synchronous what provides a big efficiency of 100%. However, the synchronous transmission needs a synchronizer...
The Internet of Things revolution requires long-battery-lifetime, autonomous end-nodes capable of probing the environment from multiple sensors and transmit it wirelessly after data-fusion, recognition, and classification. Duty-cycling is a well-known approach to extend battery lifetime: it allows to keep the hardware resources of the micro-controller implementing the end-node (MCUs) in sleep mode...
Reference drivers for charge-redistribution SAR ADCs require significant area and/or power. In this work, a low-power and area-efficient passive reference-voltage driving scheme for charge-redistribution SAR ADCs is proposed. An on-chip decoupling capacitor is pre-charged to a reference voltage during tracking phase and utilized to drive the DAC passively during conversion. The reference-voltage drops...
A 12 b 600 MS/s 2 × TI SAR ADC achieving 60 dB SNDR at Nyquist is presented. Time-interleaving errors are calibrated in the background by using a linear but noisy reference ADC. A test chip demonstrates that interleaving spurs are reduced to below −70 dBFS using an off-chip least-mean-squares (LMS) algorithm. The reference ADC is an 8 b SAR with reduced sampling capacitance and input amplitude. This...
CPU-GPU heterogeneous systems are emerging are emerging as architectures of choice for high-performance energy-efficient computing. Designing on-chip interconnects for such systems is challenging: CPUs typically benefit greatly from optimizations that reduce latency, but rarely saturate bandwidth or queueing resources. In contrast, GPUs generate intense traffic that produces local congestion, harming...
Maximizing bandwidth utilization of optical onchip interconnects is essential to compensate for static power overheads in optical networks-on-chip. Shared optical buses were shown to be a power-efficient, modular design solution with tremendous power saving potential by allowing optical bandwidth to be shared by all connected nodes. Previous proposals resolve bus contention by scheduling senders sequentially...
Synchronization has become a main concern in communication and control systems during the last years. Although there are several standard mechanisms to accomplish timing requirements, development and improvement of high synchronization technologies is required to obtain better performance and quality of service. In this context, the enhanced version of IEEE 1588v2 synchronization protocol, known as...
This work presents a 180-nm CMOS bandpass ΣΔ Analog-to-Digital Converter (ADC) developed to fulfill the specifications of a fully-integrated receiver for Magnetic Resonance Imaging (MRI). CMOS integration of a multichannel digital receiver would increase the quality of the image without the need of using many coaxial cables to connect the RF coils (located close to the patient) with the digitizing...
Oversampled continuous-time analog-to-digital converters are on the verge of surpassing the bandwidth of their discrete-time counterparts as their sampling rates continue to increase while recent innovative architectures have reduced their oversampling ratios. This paper outlines several architectures that have led to these improvements, which include single-loop ΔΣ modulators, cascaded or MASH ΔΣ...
Embedded multi core systems are implemented as systems-on-chip (SoC) that rely on packet store-and-forward networks-on-chip (NoC) for communications. These systems do not use busses nor global clock. Instead routers are used to move data between the cores and each core uses its own local clock. This implies concurrent asynchronous computing. Implementing algorithms in such system is very much facilitated...
In this paper, a 9-bit 1.3 GS/s single channel SAR ADC is presented. In conventional SAR ADCs, the capacitive DAC size grows exponentially with respect to converter resolution. This results in both signal bandwidth and conversion speed reduction. The proposed architecture implements binary search through a redundant capacitive DAC for the 5 first MSBs and through programmable comparator thresholds...
A displacement-to-digital converter (DDC) based on inductive (eddy-current) sensor is presented. The sensor is embedded in a self-oscillating front-end, whose 145MHz output is then digitized by a ratiometric ΔΣ ADC. Over a 10μm range, the DDC achieves 1.85nm resolution (1.02 pH), in a 2kHz bandwidth. It draws 9.1mW from a 1.8 V supply making it the most energy-efficient ECS interface ever reported.
A 10-bit 2GS/s time-interleaved SAR ADC with low-complexity background timing skew calibration is presented. 10% of the area is utilized for the interleaving mismatch estimation and correction. The ADC achieves −64dB mismatch spur and 50.1dB SNDR at Nyquist rate, with 10.4mW power consumption and 0.014mm2 area in 16nm.
Conventional dynamic element matching limits the continuous time ΣΔ ADC architecture at high speeds. This work introduces a Time-Interleaved Reference Data-Weighted-Averaging (TI-RDWA) architecture that breaks the speed limitation of the traditional DEM decoder. Time-interleaving eliminates the reference voltage settling bottleneck, enabling DWA operation at 5 GHz, while still achieving the benefits...
This paper describes a switched capacitor, 3rd order MASH 2-1 ΣΔ modulator, for signals with a bandwidth of 20kHz, using passive integrators implemented based on the ultra incomplete settling (UIS) concept. The UIS concept requires RC time constant values much larger than the clock period. Due to the low signal bandwidth the clock frequency is 10 MHz, which would result in large resistors and capacitors...
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