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The popularity of web based social networks is rapidly increasing nowadays. These solutions allow managing relationships online. There are also several mobile solutions to these networks but they are mainly limited to reaching the services of the social network from the mobile device. The fact, that the phonebook of the mobile phones also represents social relationships, can be used for detecting...
In this paper the design and implementation of a delay-locked loop based temperature compensated MEMS clock is presented. The system is providing a temperature compensated 48 MHz clock signal for the range of - 40 to 85°C. The temperature compensation is achieved by a combination of initial and an autonomous background calibration. The main design guidelines have been on high integration level and...
This paper describes a digital-to-time converter (DTC) architecture that can be used as a fine interpolator in a time-to-digital converter (TDC) or as an adjustable delay in clock deskewing, for example. The new architecture of the DTC achieves adjustable sub-ps-level resolution with high linearity in ns-level dynamic range. The propagation delay adjustment is implemented by digitally controlling...
Minimizing power consumption without compromising speed in any integrated circuit (IC) is a challenge. Employing multiple supply voltages (multi-Vdd) is an effective technique to achieve this. In order to minimize the power dissipation in an integrated circuit, voltage level converter circuits are required. There are two novel multi-threshold voltage (multi-Vth) based level converters are proposed...
An improved Dynamic, Partial and self reconfigurable interconnection network (Hybrid-2 Network) is presented for Dynamically Reprogrammable Resource Array (DRRA), which is a Coarse Grain Reconfiguration Architecture (CGRA). To justify the design decision, Hybrid-2 network implementation is compared against the possible implementations using Multiplexer, NoC, Crossbar and already published Hybrid-1...
Network-on-Chip (NoC) has become a widely accepted on-chip communication architecture which provides a promising solution to integrate a large number of components on a single chip. However, with the increasingly higher performance demands for on-chip systems, NoCs are facing several critical challenges such as wire delay and power consumption. Therefore, in this paper, we explore different cache...
In most articles dataflow in computer networks is described as a transfer function. Numerators, denominators and delay times give behaviors of these systems. Some systems show linear features, others have non-linear ones. All descriptions have some special results. Some of them present linear aspects of transfers, while other ones look for bottlenecks of the networks or prove stability of the systems...
The paper focuses on the design of a Network-on-chip based programmable and partitionable distributed memory architecture which can be integrated with a Coarse Grain Reconfigurable Architecture (CGRA). The proposed interconnect enables better interaction between computation fabric and memory fabric. The system can modify its memory to computation element ratio at runtime. The extensive capabilities...
Along with the economic development, cities are increasingly congested in China. In order to eliminate peak-hour congestion, many cities establish priority lanes such as bus lanes and Olympic lanes. Although priority lanes could help Local Authorities gain its short-term management objectives, at the same time, it would greatly infringe on the legitimate rights of other vehicles and waste the scarce...
A differential delay cell with complementary current control to extend the control voltage range as well as the operation frequency is proposed for high speed and wide tuning range voltage-controlled ring oscillator (VCRO). The complementary current control mitigates the restriction that control voltage can not operate at full range in a conventional VCRO. A three-stage VCRO is constructed for verifying...
This paper presents the power-performance trade off of three different cache compression algorithms. Cache compression improves performance, since the compressed data increases the effective cache capacity by reducing the cache misses. The unused memory cells can be put into sleep mode to save static power. The increased performance and saved power due to cache compression must be more than the delay...
The aim of the presented work is to improve the quality of testing of SoC digital cores surrounded with test wrappers. The paper presents a new effective delay fault test generation method for the transition faults based on the skewed-load test. The generated delay fault test can be applied to a SoC core through a test wrapper architecture with only a simple boundary scan chain. This eliminates the...
In order to eliminate accident, reduce congestion and improve the efficiency of the traffic circle, three effective and feasible methods are proposed.As an example,the traffic circle flow of the circle in Xiamen China is simulated by these methods above using VISSIM soft.The results of simulation show that three methods applied to different traffic flow each,then we did further simulations to the...
Computerized interlocking systems have been studied for many years. Available interlocking systems mainly are centralized control systems. The great progress of distributed control technology and intelligent terminals make it possible to develop distributed interlocking system. To standardize operations of devices in distributed railway signaling system, this article takes the process of train entering...
Integrating repetitive control and RBF neural network PID control , a novel control scheme for DC servo system is proposed for the high accuracy of Oscillating Mirrorsystem . The repetitive control is used to improve the steady-state characteristi of the control serosystem and enhance its ability to withstand the disturbance with same frequency; the RBF neural network PID control is used to enhance...
The main contribution of this paper is to present a new stability criterion of a kind of uncertain systems with time-varying delay. While the system matrices endure segment uncertainty, we show that there is an extreme criterion for the asymptotic stability of the given systems. Such result make it possible to check several vertex conditions. It is proved that, under our assumption, the interval system...
Porting applications to Distributed Computing Infrastructures (DCIs) is eased by the use of workflow abstractions. Yet, estimating the impact of the execution DCI on application performance is difficult due to the heterogeneity of the resources available, middleware and operation models. This paper describes a workflow-based experimental method to acquire objective performance comparison criterions...
A Vernier Gate-Ring-Oscillator (GRO) Time to Digital Converter (TDC) is proposed and implemented in 90-nm CMOS process technology. It utilizes two GRO chains as the delay lines. The time resolution is determined by the difference between two delays, so not limited by the process. Moreover, the quantization noise can be first-order shaped by the gated behavior in the oscillators, which further improves...
Massive parallel computing performed on many-core Network-on-Chips (NoCs) is the future of the computing. One feasible approach to implement parallel computing is to deploy multiple applications on the NoC simultaneously. In this paper, we propose a multi-application mapping method starting with the application mapping which finds a region on the NoC for each application and then task mapping which...
Time synchronization is one of the key points in distributed real-time computer system. At first, a time synchronization method under 1PPS signal is put forth. Secondly, two kinds of relevant synthetic disturbance are analyzed, and time synchronization logic is studied to cope with the disturbance. Arena software is chosen to model and simulate the time synchronization procedure. At last, the whole...
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