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A technique is described for the automatic insertion of fault models into VHDL gate models, using a specific algorithm to calculate fault coverage. This procedure does not require any modification to the structural description of a circuit using these models. Additional optimized algorithms are added to illustrate better calculation of fault coverage of a VHDL based combinational logic circuit.
Transient faults have become increasingly observable in combinational logic. This is due to the weakening of some inherent protective mechanisms that logic traditionally holds against such flawed spurious events. One of the aforementioned mechanisms relates to the propagation of transient faults along sensitizable paths. Existing literature that relies on logic simulation under estimates the number...
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