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This paper proposes a method to compute delay values in 3-valued fault simulation for test cubes which are test patterns with Xs. Because the detectable delay size of each fault by a test cube is fixed after assigning logic values to the Xs in the test cube, the proposed method computes a range of the delay values of the test patterns covered by the test cube. By using the proposed method, we can...
IR-drop problem during test mode exacerbates delay defects and results in false failures. In this paper, we take the X-filling approach to reduce IR-drop effect during at-speed test. The main difference between our approach and the previous X-filling methods lies in two aspects. The first one is that we take the spatial information into consideration in our approach. The second one is how X-filling...
Since scan testing is not based on the function of the circuit, but rather its structure, scan testing is considered to be a form of over testing or under testing. It is important to test VLSIs using the given function. Since the functional specifications are described explicitly in the FSMs, high test quality is expected by performing logical fault testing and timing fault testing. This paper proposes...
Latest VLSI circuits face the problem of power dissipation not only in design phase but also during testing phase. Power dissipation during testing may be increased up to three times more than that during normal operation. Testing power, testing time and test area overhead are the critical parameters to be optimized for large and complex VLSI circuits. Scan architectures are widely used in testing...
Sets of Pairs of Functions to be Distinguished (SPFD) is a functional flexibility representation method that was recently introduced in the logic synthesis domain, and promises superiority in exploring the flexibility offered by a design over all previous representation methods. In this work, we illustrate how the SPFD of a particular wire reveals information regarding the number of potential transient...
The objective of using logic BIST for online and periodic testing is to identify defects, like opens, resulting from the wear and tear of the circuit. We have shown that existing test sets have a low coverage for open defects located in scan flip-flops, even though such defects may affect functional operation. Existing Logic BIST structures suffer from the same limitations. A novel Logic BIST architecture...
In this paper, we present a novel technique for online testing of feedback bridging faults in the interconnects of the cluster based FPGA. The detection circuit will be implemented using BISTER configuration. We have configured the Block Under Test (BUT) with a pseudo-delay independent asynchronous element. Since we have exploited the concept of asynchronous element known as Muller-C element in order...
This paper presents a combinational test generation method for transition faults in acyclic sequential circuits. In this method, to generate test sequences for transition faults in a given acyclic sequential circuit is performed on its extend time-expansion model. The model is composed of two copies of time-expansion model of the given circuit and extends in the close two sequences to generate 2 vectors...
This paper proposes a novel type of modified Booth multiplier and generates constant test pairs for single transition delay faults (TDFs) in multipliers of various sizes. All TDFs of the multipliers at cell and gate levels are C-testable with 10 and 27 patterns, respectively. These patterns can be generated by using a linear feedback shift register or a finite state machine, requiring a modest increase...
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