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Using automatic instead of automated tools is assumed to significantly reduce timing budgets needed for the actualization. However, it seems to be not always the case, especially if we consider the complete actualization cycle. The article presents an investigation of the time needed for the information base actualization when using separate automated or automatic tools, as well as the time needed...
Model-based testing of embedded real-time systems is challenging because platform-specific details are often abstracted away to make the models amenable to various analyses. Testing an implementation to expose non-conformance to such a model requires reconciling differences arising from these abstractions. Due to stateful behavior, naive comparisons of model and system behaviors often fail causing...
Wireless LANs have been widely used to carry out a system to access Internet. WLAN security becomes mission one, especially a new type of attacks called covert channel based attack surfaced over the past few years. This attack uses different data rates provided in WLAN to transmit a secret message. Detecting this covert channel could be difficult due to existence of rate diversity in 802.11 WLAN....
Within the aviation industry RTCA DO-254 is the design assurance process for safety-critical airborne electronic hardware development. Safety-critical hardware (DAL A or B) requires the application of additional advanced verification techniques such as Elemental Analysis to ensure that elements of the design are adequately verified. This paper compares the verification processes currently used in...
When software developers make changes to a program, it is possible that they will introduce faults into previously working parts of the code. As software grows, a regression test suite is run to ensure that the old functionality still works as expected. Yet, as the number of test cases increases, it becomes more expensive to execute the test suite. Reduction and prioritization techniques enable developers...
Through the analysis of 20 Chinese national boxing athletes’ physical capacity testing index, the author suggest that???50m running, 30 second squat, 400m running, 15 second left rotation, 30 second sit-up, 3000m running and 1 minute sandbag striking can be consider as seven representative testing items among other components. In addition, 600m running, standing long jump, 1 minute skipping, 30 second...
Recently, software size becomes larger, and consequently, not only a software developer but also a software purchaser suffers considerable losses by software project failure. So avoiding project failure is also important for purchasers. Project monitoring with a purchaser and a developer (stakeholders) is expected for the purchaser to suppress risk of project failure. It is performed by sharing software...
This paper presents principles and results of dynamic testing of an SRAM-based FPGA using time- resolved fault injection with a pulsed laser. The synchronization setup and experimental procedure are detailed. Fault injection results obtained with a DES crypto-core application implemented on a Xilinx Virtex II are discussed.
Simultaneous switching noise (SSN) is an important issue for the design and test and actual ICs. In particular, SSN that originates from the internal logic circuitry becomes a serious problem as the speed and density of the internal circuit increase. In this paper, an on-chip monitor is proposed to detect potential logic errors in digital circuits due to the presence of SSN. This monitor checks the...
Present and future semiconductor technologies are characterized by increasing parameters variations as well as an increasing susceptibility to external disturbances. Transient errors during system operation are no longer restricted to memories but also affect random logic, and a robust design becomes mandatory to ensure a reliable system operation. Self-checking circuits rely on redundancy to detect...
In many DSP applications (image and voice processing, baseband symbol decoding in high quality communication channels) several dBs of SNR loss can be tolerated without noticeable impact on system level performance. For power optimization in such applications, voltage overscaling can be used to operate the arithmetic circuitry slower than the critical circuit path delay while incurring tolerable SNR...
The soft-error vulnerability of flip-flops has become an important factor in IC reliability in sub-100-nm CMOS technologies. In the present work the soft-error rate (SER) of a 65-nm flip-flop has been investigated with the use of alpha-accelerated testing. Simulations have been applied to study the flip-flop SER sensitivity in detail. Furthermore, an easy-to-use approach is presented to make an accurate...
In this paper, we present a new technique to improve the reliability of H-tree SRAM memories. This technique deals with the SRAM power-bus monitoring by using built-in current sensor (BICS) circuits that detect abnormal current dissipation in the memory power-bus. This abnormal current is the result of a single-event upset (SEU) in the memory and it is generated during the inversion of the state of...
Timing-error detection and recovery circuits are implemented in a 65 nm resilient circuit test-chip to eliminate the clock frequency guardband from dynamic supply voltage (VCC) and temperature variations as well as to exploit path-activation probabilities for maximizing throughput. Two error-detection sequential (EDS) circuits are introduced to preserve the timing-error detection capability of previous...
This paper investigates and simulates a coloured stochastic Petri nets model for depth evaluation intrusion detection. Network attack behaviors are very complexity sometimes, it is difficult to capture all of them. In this paper, we could realize what them happened with analyzing and simulating an intrusion. The experimental results demonstrated that the CSPN model approach was an efficient and helpful...
This paper describes a methodology for building a reliable internet core router that considers the vulnerability of its electronic components to single event upset (SEU). It begins with a set of meaningful system level metrics that can be related to product reliability requirements. A specification is then defined that can be effectively used during the system architecture, silicon and software design...
According to the specified standard of airborne Photogrammetry, digital airborne cameras must have higher performance than ordinary civil cameras, which must shoot with shorter time interval and will generate huge data stream. In this paper, a digital airborne camera is designed and implemented in a single FPGA chip as a SOPC approach. The functions of image acquisition, storage and display are implemented...
Summary form only given. Tools that feature MSC do not have the ability to check model or implementation executions against the specified behavior. We present a method for observing the behavior of timed systems specified using Message Sequence Chart Graphs (MSC-Graphs) (a simplified version of ITU Z.120 notation). We believe that a log-analyzer and a run-time monitor based on MSC-Graphs are practical...
Considered here is the possibility of application of synchronizing devices in SDH transport networks. Such devices use the signals of radio navigation satellite systems GPS and GLONASS. Presented are the results of instability measurement for the timing signal of an SN-3836 device. The paper describes basic principles of creation of a system for timing signals monitoring.
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