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Network-on-chip (NoC) is emerging as an effective architecture which address the shortcomings of traditional bus-based System-on-chip (SoC). Since its better properties, such as the lower power consumption, smaller size and higher scalability, mesh is often regarded as an effective topology for NoC design. In this paper, we propose a double-layer sparse honeycomb topology as a terrific design option...
This paper presents a router structure for Network-on-Chips called Quad Router which benefits from communication locality. The router can be shared among more than one Processing Element (PE), so the average hop count of a packet is decreased. This structure consists of eight input buffers and eight output ports by which two different topologies are introduced called Double-Link Mesh (DLM) and Crossbar...
The communication infrastructure of a complex multicore system-on-a-chip is getting an increasing fraction of the overall chip area. According to the International Technology Roadmap for Semiconductors, killer defect density does not decrease over successive technology generations. For this reason, the probability that a manufacturing defect affects the communication system is predicted to increase...
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