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A flat-gain design of an ultra wide-band CMOS amplifier is proposed and simulated in 90 nm CMOS process. Inductive degeneration is applied to reduce noise figure without significantly raising the architecture's power requirement. Additionally, a resistive shunt feedback technique is applied with an RL peaking load to flatten the gain throughout design band. This topology allows the amplifier to have...
A fully integrated variable gain amplifier circuit is reported in this paper. The amplifier is based on an integrating topology allowing the gain to be controlled by the timing of a clock signal. The recording of physiological signals such as the electroneurogram (ENG) or electromyogram (EMG) is a targeted application. Therefore, low-noise performance and low power consumption are important. Simulated...
A low phase noise, small power dissipation and small sized Ka-band Triple Push Coupled Pair using 0.18 μm CMOS technology is described. The VCO operated can be tuned between 37.3 GHz and 40.1 GHz and has low phase noise of -107 dBc/Hz at a 1 MHz offset. The Figure of merit (FOM) is -184.8 dBc/Hz and the power-frequency tuning-normalized figure-of-merit (PFTN) is -11.8 dB. The power consumption of...
In this paper, a fully integrated 42-GHz VCO in 90 nm CMOS is described. This VCO is designed for use in licensed E-band (i.e., 81-86 GHz) transceiver systems. In contrast to conventional LC-VCO topologies, a standing wave transmission line resonator instead of a lumped LC tank is employed to provide an extended output frequency range and relatively low phase noise. A slow wave coplanar waveguide...
This paper presents a 0.8 V class-AB linear operational transconductance amplifier (OTA) using DTMOS for high-frequency applications. The circuit employs positive feedback to enhance the input impedance, and feed-forward technique to suppress the common-mode gain. The circuit is designed using 0.18 μm CMOS technology under 0.8 V supply. The simulation results show rail-to-rail input/output swing,...
Modern communication networks demand power amplifiers (PAs) which are efficient and have low distortion. The common drain amplifier has the potential to become a linear amplifier with good efficiency, when biased at or above class-B. The main challenge is to provide unconditional stability while still maintaining adequate transducer gain so that the power added efficiency (PAE) will not be compromised...
This paper presents a 0.5 V pseudo fully differential CMOS op-amp with rail-to-rail input/output swing. The circuit is designed based on class AB input and output stages. In the design, quasi FGMOS transistors are employed. The proposed amplifier is designed using 0.18 μm CMOS technology, and the simulation results show rail-to-rail input and output swings. The open-loop gain and gain-bandwidth product...
An ultra low voltage rail-to-rail DTMOS voltage follower is presented. The circuit is developed based on a complementary source follower with a common-source output stage. The circuit is designed using a 0.13 μm CMOS technology and SPICE is used to verify the circuit performance. The voltage follower can drive ± 0.25 V to the 500 Ω with the total harmonic distortion (THD) of 0.4% at the operating...
This paper presents the design of a 2-16 GHz ultra wide band low noise amplifier (UWB LNA). The proposed LNA has a gain of 11.5 ± 0.85 dB with NF less than 2.82 dB. Good input and output impedance matching, good isolation and linearity are achieved over the operating frequency band. The proposed UWB LNA consumes 18.14 mW of power from 1.8 V supply. This UWB LNA is designed and simulated in 0.18 μm...
This paper presents a simple, ultra-compact and isolated gate driver system used to drive power switches. Using two legs of a CMOS inverter, a high frequency transformer and two zener diodes connected with the gate of power switch, this driver provides an optimal gate driver waveform with a high gate voltage to switch on the transistor, and a negative bias gate voltage during OFF state. In the paper,...
In this paper, a Q-band common source low noise amplifier (LNA) using 90-nm standard RF-CMOS technology is proposed. The design methodologies for millimeter-wave (MMW) amplifiers are discussed. The post layout simulation results show that S11 is lower than -14 dB and S22 is -11 dB at the peak gain of 14.6 dB at 37.5 GHz with 9.4 GHz bandwidth, the minimum noise figure is lower than 5.5 dB, the input...
In this paper, a low voltage low power (LPLV) current output stage (COS) with high CMRR is proposed. A novel common mode feedback (CMFB) technique is exploited to provide high CMRR. That is done by summing the main common mode signal and its opposite polarity one which provides over 112 dB of CMRR in 0.18 μm CMOS technology of TSMC. The circuit operates with very low supply voltages of ±0.5 V and...
We present the design of an analog-to-information (A2I) converter consisting of parallel analog processing channels, whose output is sampled by traditional analog-to-digital converters (ADCs). The architecture employs a reconfigurable analog front-end that modulates the signal of interest with a high-speed digital chipping sequence and integrates the result prior to sampling at a low rate. This front-end...
This paper presents a wide tuning rang mm-wave VCO (voltage controlled oscillator) fabricated in IBM 90-nm CMOS technology. The VCO can be tuned from 31.4 GHz to 42.2 GHz and utilizes a differential tuning mechanism based on varactors and switched capacitors. A switched current source is used to improve the performance of the VCO when an MIM (metal-insulated-metal) capacitor is switched in the LC...
A 24 GHz Class-A amplifier is designed in 0.13 μm CMOS technology. The matching network for the cascode amplifier is implemented by microstrip lines that have been implemented in small space by meandering. The amplifier delivers 12.5 dBm power to a 50 Ω load from a 2 V supply. A maximum Power Added Efficiency (PAE) of 30% is achieved at 1-dB compression point (P1dB).
This paper presents the design of a 12-bit 8MSamples/s (MSPS) current-steering digital-to-analog converter (DAC) using 0.13 μm CMOS technology. The proposed DAC has adopted a segmented architecture in order to achieve a minimized die area and optimized performance. The current steering network consists of binary weighted current sources for the 8 least significant bits (LSBs) and a unary current cell...
A smart meter is essential for realizing the smart grid. In order to further reduce the energy loss in the power grid, an extremely fine-grain power monitoring system is desirable and it will require an enormous number of low-cost power meters. Existing power meters, however, do not meet the cost and size requirements. On the other hand, organic devices on flexible films have great potential to realize...
Although Si CMOS PAs for mobile applications have demonstrated specification-compliant performance over the last several years, Si CMOS has not been widely employed in cellular PA applications due to certain inferior properties of its power capability, PAE, and breakdown to its counterparts such as GaAs and SiGe BJTs. However, research conducted in the past decade has enabled commercially available...
This paper introduces an EER 90 nm CMOS experimental prototype switched capacitor power amplifier (SCPA) that achieves high output power, efficiency and linear output-power control using a switched-capacitor-based switching PA without the use of a supply modulator. While amplifying 64-QAM OFDM modulation with a 20 MHz signal bandwidth it achieves an average output power of 17.7 dBm, an average PAE...
One of the remaining challenges in implementing CMOS 60GHz radios is to cover longer communication distance as the high path loss at mm-Wave frequencies demands higher EIRP, which in turn requires considerable design effort on the transmitter. In addition, to comply with the OFDM transmitting mode of the IEEE 802.15.3c standards, the power amplifier (PA) must be capable to handle a peak power level...
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