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With the increase in the levels of on-chip integration, the number of functional units integrated onto a single chip is rapidly increasing and as a result, the logic delays are decreasing due to faster transistors. At the same time, the local interconnect delays improve because the physical size of the circuit blocks decrease and the local interconnect spans shorter distances. On the other hand, the...
On-chip inductive effects are becoming predominant in deep submicron (DSM) interconnects due to increasing clock speed, circuit complexity and decreasing interconnect lengths. Inductance causes noise in the signal waveforms, which could adversely affect the performance of the circuit and signal integrity. The traditional analysis of crosstalk in a transmission line begins with a lossless LC representation,...
Due to the requirement of high data transmission rate, bandwidth has become an important performance parameter for high speed VLSI design. In order to have the maximum data transfer possible through the on-chip data buses, the bandwidth of the interconnect has to be precisely modeled. At very high frequency (of the order of few GHz) both inductance and conductance matrices become equally important...
In this paper, we introduce a very high bandwidth proximity communication technique for Stacked LSIs. This technology is based on transmission line coupling between two differential pairs in the metal layers of each chip and can be implemented without modifying conventional chip fabrication process. We have demonstrated its feasibility using a single chip in which coupled two differential pairs of...
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