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In this paper, we present the design and implementation of a BRAM-based multiported register file with arbitrary number of read and write ports. In order to avoid the conflicts associated with write ports, we present a register renaming technique that is applied between the compiler and the assembler. This technique enables the utilization of a banked-BRAM register file as a true multiported register...
Reconfigurable instruction set processors are the next generation processors which can adapt their instruction sets through a reconfiguration process in their hardware according to the demand of the application being under execution on them. In this way the processors adapt the hardware which is the most suitable solution for the running application and hence it accelerates the performance gain. The...
Due to the potential enhancements in the execution of software based applications shown by Reconfigurable Instruction Set Processors (RISPs), reconfigurable computing has become a subject of great deal of research in the field of computer sciences. Its key feature is the ability to perform the computations in hardware to increase the performance on one hand while retaining much of the flexibility...
This paper presents a novel high-speed behavioural simulator (software-based emulator) for reconfigurable instruction cell based processors. These architectures are particularly suited to providing low-power, low-cost implementations of applications in a streaming environment, such as image signal processing, video playback, or base-band signal processing. As a result, many realistic applications...
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