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In this paper a method to estimate the leakage power consumption of CMOS digital circuits taking into account input states and process variations is proposed. The statistical leakage estimation is based on a pre characterization of library cells considering correlations (ρ) between cells leakages. A method to create cells leakage correlation matrix is introduced. The maximum relative error achieved...
Wakeup time is an important overhead that must be determined for effective power gating, particularly in logic clusters that undergo frequent mode transitions for run-time leakage power reduction. In this paper, a semiempirical model for virtual supply voltage in terms of basic parameters of the power-gated circuit is presented. Hence a closed-form expression for estimation of wakeup time of a power-gated...
This paper addresses the crucial problem of static power reduction for circuits implemented in nano-CMOS technologies. Its solution requires accurate and rapid power estimation, but the known power simulators are not accurate and quick at the same time. The paper proposes and discusses a new rapid and very accurate leakage power estimation method and related simulator. The maximum estimation error...
Accurate leakage current estimation in the early phase of digital IC synthesis is an increasingly critical step in the design flow. We present a logic-level estimation approach, suitable for implementation in HDL models or as an off-line tool, supporting separate estimation of the leakage components (sub-threshold, gate tunneling, reverse junction BTBT) including pattern dependency, stacking effects...
The Monte-Carlo simulation based leakage current analysis provides very accurate results, but it has high computational complexity. In this paper, we present the Monte-Carlo based leakage estimation method, which is implemented on a GPU and a CUDA platform. Thereby using the Monte-Carlo method on a GPU, we can expect not only high simulation accuracy but also high estimation efficiency. Because a...
Power consumption has become a key constraint in VLSI designs. Leakage current becomes a dominant part of the total power dissipation. In addition, with technology scaling into sub-50 nm regime, one of the main design challenges in the presence of process variations is to cope with the uncertainties in timing and power. Since the leakage current is highly dominated by process variations, the statistical...
A Trojan attack maliciously modifies, alters, or embeds unplanned components inside the exploited chips. Given the original chip specifications, and process and simulation models, the goal of Trojan detection is to identify the malicious components. This paper introduces a new Trojan detection method based on nonintrusive external IC quiescent current measurements. We define a new metric called consistency...
The paper presents a detailed study on the idle leakage reduction techniques on partially depleted silicon-on-insulator (PD-SOI) CMOS SRAM. The most promising leakage reduction techniques that have been proposed are introduced, analyzed and compared into 65 nm low-power PD-SOI technology, taking into account all the SOI specific effect. Especially, it is shown that the leakage reduction techniques...
The dramatic increase in leakage current, coupled with the swell in process variability in nano-scaled CMOS technologies, has become a major issue for future IC design. Moreover, due to the spread of leakage power values, leakage variability cannot be neglected anymore. In this work an accurate analytic estimation and modeling methodology has been developed for logic gates leakage under statistical...
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