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In this work, the power-rail ESD clamp circuit fabricated in 130 nm CMOS process is investigated. In order to improve the ESD protection ability, the power-rail ESD clamp circuit with gate-substrate-triggered is proposed. By comparing with the other two techniques, gate-driven and substrate-triggered, it is shown that the secondary breakdown current of the power-rail ESD clamp circuit with gate-substrate-triggered...
ESD protection design for CMOS RF integrated circuits is proposed in this paper by using the stacked polysilicon diodes as the input ESD protection devices to reduce the total input capacitance and to avoid the noise coupling from the common substrate. The ESD level of the stacked polysilicon diodes on the I/O pad is restored by using the turn-on efficient power-rail ESD clamp circuit, which is constructed...
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