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We present a novel hardware algorithm for scheduling tasks with dependency constraints on multicore architectures. This algorithm provides a deadlock-free scheduling over a large class of architectures by employing a generalization of a fundamental algorithm by Tomasulo. Performance measurements show that the proposed algorithm can deliver higher performance than a large increase in the number of...
In order to construct the most suitable embedded software development environment, we design and implements the Retargetable Tool Suite for Embedded Software (RTS-ES) composed of target code generator, low power/energy optimizer, system simulator and debugger through the proposed Embedded Processor Description Language (EPDL).
Due to their reconfigurability and their high density of resources, SRAM-based FPGAs are more and more used in embedded systems. For some applications (Pay-TV,Banking, Telecommunication ...), a high level of security is needed. FPGAs are intrinsically sensitive to ionizing effects, such as light stimulation, and attackers can try to exploit faults injected in the downloaded configuration. Previous...
Performance evaluation techniques for fundamental graphics algorithms and for algorithms to be used in multimedia and embedded systems are investigated. Models of computation considering only arithmetic and logic operations taken on input data are regarded as inadequate for processors with instruction-level parallelism. For experimental evaluation of graphics algorithms clock-cycle counting is found...
The reliability of advanced embedded non-volatile memories has been discussed using the 2T-FNFN devices example. The write/erase endurance and the data retention are the most important reliability parameters. The intrinsic reliability mechanisms can be addressed through single cell evaluation, while the cell-to-cell variation determines the product level reliability. The cell-to-cell variation can...
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