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article

Modelling and mitigation of single-event upset in CMOS voltage-controlled oscillator

Satyam Shukla, S S Gill, H S Jatana, Varun Nehru, more

Sādhanā > 2018 > 43 > 11 > 1-10

Single-event effects (SEEs) have been the primary concern in study of radiation effects since late 1970s with the discovery of soft errors in terrestrial and space environments. The interaction of a single ionized particle with electronic devices leads to SEEs. In this paper, single-event upset (SEU) on CMOS devices in designing of a voltage-controlled oscillator (VCO) is analysed. Further, mitigation...

article

Microw(h)att?! Ultralow-Power Six-Port Radar: Realizing Highly Integrated Portable Radar Systems with Good Motion Sensitivity at Relatively Low Cost

Fabian Lurz, Fabian Michler, Benedict Scheiner, Robert Weigel, more

IEEE Microwave Magazine > 2018 > 19 > 1 > 91 - 98

Short-range noncontact microwave radar systems have undergone significant development in recent years [1]. Driven by advances in modern monolithic microwave integrated circuitry, printed circuit board (PCB) technologies, and embedded computing, highly integrated portable radar systems with good motion sensitivity can today be realized at relatively low cost. Radar systems have emerged in a variety...

article

A $K$ -Band High-Efficiency VCO Using Current Reused Technique

Yu-Teng Chang, Hsin-Chia Lu

IEEE Microwave and Wireless Components Letters > 2017 > 27 > 12 > 1134 - 1136

In this letter, we present a high-efficiency CMOS voltage control oscillator (VCO) at K-Band. In order to achieve high efficiency, we adopt center-tapped transformer and current reused technique to integrate cross couple pair and buffer amplifier. In addition, we put buffer amplifier gate bias at class AB to enhance efficiency. VCO tuning range is from 22.35 to 25.31 GHz. Across the VCO frequency...

article

A Hybrid Self-Tracking Receiver Implementation With Direction-of-Arrival Estimation for Retro-Directive Antenna Systems

Andreas Winterstein, Achim Dreher

IEEE Transactions on Microwave Theory and Techniques > 2017 > 65 > 12-2 > 5422 - 5431

Self-tracking receivers have been suggested for satellite and mobile communication applications. In this paper, we propose and demonstrate an array receiver (Rx) architecture based on phase-locked loops. The system is capable of automatically tracking a moving source and providing direction-of-arrival (DOA) estimates calculated from array signal phase differences. After deriving the system transfer...

article

Ultralow-Power Radar Sensors for Ambient Sensing in the ${V}$ -Band

Stefan Shopov, Mekdes G. Girma, Juergen Hasch, Ned Cahoon, more

IEEE Transactions on Microwave Theory and Techniques > 2017 > 65 > 12-2 > 5401 - 5410

The design considerations and circuit topologies of a family of ultralow-power fundamental-frequency and second-harmonic 60-GHz radar sensors are described. The single-chip sensor architecture features four low-noise-matched receivers, either a fundamental-frequency 60-GHz voltage-controlled oscillator (VCO) or 30-GHz VCO + doubler, and a static divide-by-8192 chain which is turned OFF 95% of the...

article

A 0.9–2.6 GHz Cognitive Radio Receiver With Spread Spectrum Frequency Synthesizer for Spectrum Sensing

Lei Qiu, Supeng Liu, Ying Zhang, Yao Zhu, more

IEEE Sensors Journal > 2017 > 17 > 22 > 7569 - 7577

In this paper, 0.9–2.6 GHz receiver with spread spectrum frequency synthesizer is proposed for spectrum sensing cognitive radio system. With the presence of spread spectrum window generated by local synthesizer, the bandwidth of low-pass filter for spectrum sensing can be fixed, which alleviates the complexity of energy detection block, making it easily embedded into a transceiver chip. The proposed...

chapter

An ultra-low power 169-nA 32.768-kHz fractional-N PLL

Chun-Yu Lin, Tun-Ju Wang, Tzu-Hsuan Liu, Tsung-Hsien Lin

2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) > 45 - 48

2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)

This paper presents an ultra-low power 32.768-kHz fractional-N phase-locked loop (PLL). Several circuit techniques are adopted to facilitate low-power operation. A duty-cycled control scheme is proposed to turn off the charge pump intermittently for energy saving. In the VCO, a near-off switch is applied to implement a large resistor, leading to a lower power consumption and smaller chip area. Furthermore,...

chapter

A 65nm 376nA 0.4V linear classifier using time-based matrix-multiplying ADC with non-linearity aware training

A Anvesha, Arijit Raychowdhury

2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) > 309 - 312

2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)

A 6-bit time-based folding matrix multiplication technique for support vector machine (SVM) classification is proposed. A voltage controlled oscillator (VCO) based analog-to-digital converter (ADC) performs in-situ matrix multiplications (MM) along with analog to digital conversion. It also offers a low supply voltage of operation (down to 0.4V) and an input range of 0.8V, drawing a total of 376nA...

article

Measuring Target Range and Velocity: Developments in Chip, Antenna, and Packaging Technologies for 60-GHz and 122-GHz Industrial Radars

Efe Ozturk, Dieter Genschow, Uroschanit Yodprasit, Berk Yilmaz, more

IEEE Microwave Magazine > 2017 > 18 > 7 > 26 - 39

Increasing demand for industrial radars has spurred research aimed toward designing better transceiver (TRx) integrated circuits (ICs) combined with advanced packaging technologies [1]-[6], innovative antenna concepts, very precise wirebonding schemes [5]-[8], and high-performance baseband processing systems [9]. With a well-optimized package of such products, the resulting application fields can...

article

A 2.4-GHz 1.5-mW Digital Multiplying Delay-Locked Loop Using Pulsewidth Comparator and Double Injection Technique

Hyunik Kim, Yongjo Kim, Taeik Kim, Hyung-Jong Ko, more

IEEE Journal of Solid-State Circuits > 2017 > 52 > 11 > 2934 - 2946

In this paper, we propose a low-jitter low-power digital multiplying delay-locked loop (MDLL) with a self-calibrated double reference injection scheme. To reduce jitter, the noisy edge of the oscillator is replaced by both the rising and falling edges of the clean reference, which results in 6-dB reduction in phase noise compared with a conventional single-edge injection MDLL. Reference spur caused...

article

Clock Jitter Reduction and Flat Frequency Generation in PLL Using Autogenerated Control Feedback

Suman Bhowmik, Sambhu Nath Pradhan, Bidyut K. Bhattacharyya

IEEE Transactions on Components, Packaging and Manufacturing Technology > 2017 > 7 > 11 > 1832 - 1841

In this paper, a method has been proposed by which one can reduce the clock jitter and achieve almost flat frequency clock output from the phase-locked loop (PLL), independent of the power supply voltage fluctuation. These voltage fluctuations occur when a given chip comes out from the sleep mode to the active mode. This causes the chip to draw a hasty current, which in turn produces LdI/dt noise...

chapter

Design of a 0.52 mW −141 dBc/Hz and 450 MHz frequency synthesizer using low power and low phase noise current reuse VCO

B. Dinesh Kumar, Hitesh Shrimali

TENCON 2017 - 2017 IEEE Region 10 Conference > 2937 - 2912

TENCON 2017 - 2017 IEEE Region 10 Conference

This paper presents the design of a frequency synthesizer using phase locked loop (PLL) in a standard 130 nm CMOS technology with the supply voltage of 1.2 V. The low power and the low phase noise based current reuse VCO (CRVCO) and the frequency divider have been used to design the frequency synthesizer. The designed CRVCO gives a low power and a low phase noise performance. The designed PLL consumes...

chapter

A 77-GHz mixed-mode FMCW signal generator based on bang-bang phase detector

Jianfu Lin, Zheng Song, Nan Qi, Woogeun Rhee, more

2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) > 317 - 320

2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)

A 77-GHz mixed-mode frequency-modulated continuous-wave (FMCW) signal generator is proposed based on the bang-bang phase detector (BBPD). Instead of employing a linear digital-to-time converter (DTC), a 1-bit 3^rd-order singleloop ΔΣ modulator (SLDSM3) and a hybrid finite-impulse response (FIR) filter are utilized to suppress the quantization noise induced by the BBPD. Two-stage infinite-impulse response...

chapter

Neuromorphic Adaptive Edge-Preserving Denoising Filter

Aidana Irmanova, Olga Krestinskaya, Alex Pappachen James

2017 IEEE International Conference on Rebooting Computing (ICRC) > 1 - 6

2017 IEEE International Conference on Rebooting Computing (ICRC)

In this paper, we present an on-sensor neuromorphic vision hardware implementation of denoising spatial filter. The mean or median spatial filters with fixed window shape are known for its denoising ability, however, have the drawback of blurring the object edges. The effect of blurring increases with increase in window size. To preserve the edge information, we propose a spatial filter that uses...

chapter

A 25–28Gb/s PLL-based full-rate reference-less CDR in 0.13μm SiGe BiCMOS

Peng Zhang, Changchun Zhang, Jingjian Zhang, Yi Zhang, more

2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM) > 186 - 190

2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)

A 25–28Gb/s full-rate reference-less CDR is presented and designed in a standard 0.13μm SiGe BiCMOS process, which can be applicable to nearly all classical 100G communication protocols by multi-channel configuration. It consists mainly of a full-rate phase frequency detector, a quadrature voltage control oscillator and two voltage to current convertors with loop filters. A dual-loop topology is adopted...

chapter

A 0.6-V 200-kbps 429-MHz ultra-low-power FSK transceiver in 90-nm CMOS

Chun-Yuan Chiu, Zhen-Cheng Zhang, Tsung-Hsien Lin

2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) > 193 - 196

2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)

A 0.6-V, 200-kbps, 429-MHz ultra-low-power FSK transceiver (TRX) is presented. The receiver (RX) adopts a frequency-to-time based demodulator, which detects high or low frequency to determine data output level. The proposed RX achieves −85-dBm sensitivity at 0.1% BER and draws 0.146 mW. A 38.7% global efficiency, 429-MHz FSK transmitter (TX) is also reported in this paper. To remove the power-hungry...

chapter

A dual-channel GNSS receiver for GPS and Beidou applications

Yuze Lyu, Wei Zou, Shuang Chen

2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM) > 326 - 329

2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)

This paper presents a dual-channel GNSS receiver covering GPS and Beidou on a single chip in 0.13μm CMOS process. The receiver incorporates one reconfigurable RF front-end and two separate IF signal channels with one single fractional-N frequency synthesizer by using a ring voltage-controlled oscillator. This architecture supports an external active or passive antenna and provides the benefits of...

chapter

Design of a K-band fast hopping frequency synthesizer

Zhicheng Hu, Guolin Sun

2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM) > 137 - 140

2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)

The design and implementation of a K-band fast hopping frequency synthesizer based on DDS and PLL is described. Main technical specifications are as follows: frequency ranges from 24GHz to 27GHz, step frequency is 50MHz and lock time is less than 150ns. The parameters of loop filter and the analyses of phase noise and lock time are provided by MATLAB simulation to verify the feasibility of the design...

chapter

Concurrent VCO using capacitive coupled oscillators

Wen-Cheng Lai, Sheng-Lyang Jang, Chun-Chih Wang

2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM) > 1 - 4

2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)

This letter proposes a new concurrent CMOS voltage-controlled oscillator (VCO). The oscillator consists of two sub-VCO operates at 4GHz and 6GHz respectively. The two sub-VCOs are coupled by a pair of MIM capacitors. The proposed oscillator has been implemented with the TSMC 0.18μm BiCMOS technology. By controlling the supply voltages, the VCO has three different operational modes, capable of generating...

chapter

A −245 dB FOM 48 fs rms jitter semi-digital PLL with intrinsic temperature compensation in 130 nm CMOS

J. Anders, S. Bader, M. Dietl, P. Sareen, more

2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) > 325 - 328

2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)

In this paper, we present a temperature compensated semi-digital integer-N PLL realized in a standard 130 nm CMOS technology, which achieves 48 fs rms phase jitter and a FOM of −245 dB. The presented design improves the phase noise performance of previously presented semi-digital PLLs by replacing the ring oscillator VCO by a semi-digitally tuned LC-tank VCO. In contrast to mostly digital PLLs, the...

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VOLTAGE-CONTROLLED OSCILLATORS (4,608)
PHASE NOISE (1,874)
CMOS INTEGRATED CIRCUITS (1,572)
PHASE LOCKED LOOPS (1,396)
TUNING (883)
VCO (733)
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VOLTAGE CONTROLLED OSCILLATOR (428)
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VOLTAGE-CONTROLLED OSCILLATOR (317)
PLL (314)
SIZE 0.18 MUM (314)
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Search results

Modelling and mitigation of single-event upset in CMOS voltage-controlled oscillator

Microw(h)att?! Ultralow-Power Six-Port Radar: Realizing Highly Integrated Portable Radar Systems with Good Motion Sensitivity at Relatively Low Cost

A $K$ -Band High-Efficiency VCO Using Current Reused Technique

A Hybrid Self-Tracking Receiver Implementation With Direction-of-Arrival Estimation for Retro-Directive Antenna Systems

Ultralow-Power Radar Sensors for Ambient Sensing in the ${V}$ -Band

A 0.9–2.6 GHz Cognitive Radio Receiver With Spread Spectrum Frequency Synthesizer for Spectrum Sensing

An ultra-low power 169-nA 32.768-kHz fractional-N PLL

A 65nm 376nA 0.4V linear classifier using time-based matrix-multiplying ADC with non-linearity aware training

Measuring Target Range and Velocity: Developments in Chip, Antenna, and Packaging Technologies for 60-GHz and 122-GHz Industrial Radars

A 2.4-GHz 1.5-mW Digital Multiplying Delay-Locked Loop Using Pulsewidth Comparator and Double Injection Technique

Clock Jitter Reduction and Flat Frequency Generation in PLL Using Autogenerated Control Feedback

Design of a 0.52 mW −141 dBc/Hz and 450 MHz frequency synthesizer using low power and low phase noise current reuse VCO

A 77-GHz mixed-mode FMCW signal generator based on bang-bang phase detector

Neuromorphic Adaptive Edge-Preserving Denoising Filter

A 25–28Gb/s PLL-based full-rate reference-less CDR in 0.13μm SiGe BiCMOS

A 0.6-V 200-kbps 429-MHz ultra-low-power FSK transceiver in 90-nm CMOS

A dual-channel GNSS receiver for GPS and Beidou applications

Design of a K-band fast hopping frequency synthesizer

Concurrent VCO using capacitive coupled oscillators

A −245 dB FOM 48 fs rms jitter semi-digital PLL with intrinsic temperature compensation in 130 nm CMOS

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