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We propose a high-resolution 8-bit time-to-digital converter that uses two-level fractional difference conversion to reduce area and power consumption. Two delay-locked loops stabilize the propagation delay in the upper and lower buffer chains of the Vernier delay line that is used to make the measurement. In a transistor-level simulation using 0.35 ??m technology, this architecture achieves a resolution...
This paper discusses an architecture for an integrated ultra-low power impulse radio receiver for low data rate applications such as biomedical sensor networks. Choosing a proper system architecture allows to implement a receiver with relaxed specifications for the typical building blocks which results in a low-power implementation. Furthermore a design in 130 nm CMOS of a fully integrated ultra-low...
We demonstrate a simple, two-stage optical pulse compressor based on optical parametric amplifier using single spool of highly nonlinear dispersion-shifted fiber. 112-ps- wide pulses are compressed to 24-ps Gaussian-shaped pulses with clear eye openings.
An InAs/GaAs quantum dot saturable absorber mirror was developed to passively mode-lock a Nd:YVO4 laser at the wavelength of 1064.6 nm. CW mode-locked pulses of 24ps duration at a repetition rate of 65 MHz were obtained.
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