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In this paper we present a differential stage suitable to be used as the input stage of rail-to-rail very low-voltage opamps. The topology exploits an input level-shifter to keep the common-mode input voltage of a pseudo-differential pair constant, thus providing a constant gain over the whole input common-mode range. The main drawback of the proposed solution is the need of a switched-capacitor level-shifter,...
In this paper we present a low-power low-voltage class-AB amplifier with rail-to-rail output swing capable of operating from 0.5V to 1.0V of supply voltage, and two Sample & Hold (SHA) circuits based on this amplifier. The bias current and the bandwidth of the amplifier depend on the voltage supply, so that for low-power operation a low supply voltage can be used. The two SHAs have a nominal gain...
We present an integrated, low noise patch-clamp amplifier for biological nanopore applications. Our amplifier consists of an integrator-differentiator architecture coupled with a novel opamp design in the CMOS 0.35 μm process. The post-layout full-chip simulation shows the input referred noise of the amplifier is 0.49 pA RMS over a 5 kHz bandwidth using a verified electrical model for the biological...
By splitting the input sampling capacitor of a SigmaDelta modulator into several time-interleaved branches, FIR filtering can be incorporated into the signal transfer function. Doing so imposes little or no overhead in the design of the opamps. Simulations of a 3rd-order modulator demonstrate that up to 65 dB of anti-aliasing can be obtained with 5 time-interleaved switched capacitor branches.
In general, models at the device and circuit levels are very important in system design. Building compact models at the circuit level is complicated, needs a lot of physical information about the circuit and moreover it has a long simulation time. We present in this paper an alternative modeling methodology, black box modeling. In this technique, we need only the output behavior of the circuit. We...
This paper describes a new differential current memory cell which is based on the Miller effect and an interleaved ADC architecture. As far as the CMC is concerned, it was pointed out that the opamp design is not an issue to achieve high performances. Simulation results show good performances for sampling rates up to 20MS/s (assuming 22ns for both sampling and holding mode) and relatively large current...
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