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This paper presents a six-bit current-steering digital-to-analogue converter (DAC), which optimises the spurious free dynamic range (SFDR) performance of high-speed binary weighted architectures by lowering current switch distortion and reducing the clock feedthrough effect. A novel current source cell is implemented that comprises heterojunction bipolar transistor current switches, negative-channel...
In this paper an object of analysis and simulation modeling are the basic programmable circuits using CMOS digital potentiometers or Resistive Digital-to-Analog Converters (RDACs). Based on the analysis and principle of operation an improved SPICE-based behavioral model for RDAC potentiometers is created. The model accurately reflects resolution (wiper steps), nominal end-to-end resistance, wiper resistance,...
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