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In this paper, we propose using joint equalization and coding to improve on-chip communication speeds by signaling at rates beyond the rate governed by resistance-capacitance (RC) delay of the interconnect. Operating beyond the RC limit introduces inter-symbol interference (ISI). We mitigate the effects of ISI by employing equalization. The proposed equalizer employs a variable threshold inverter...
With the ever-increasing degrees of integration, design of communication architectures for big systems on chip (SoCs) is a challenge. The communication requirements of these large multi processor SoCs (MP-SoCs) are convened by the emerging network-on-a-chip (NoC) paradigm. To become a viable alternative IC design methodology, the NoC paradigm must address system-level reliability issues, which are...
Interconnect fabrics of multi-core systems - on-chip are confronted with increased crosstalk effects and energy dissipation. Crosstalk avoidance coding (CAC) is a promising way to reduce the coupling capacitance of the interconnect wires. We propose a method to address both crosstalk and energy dissipation in networks-on-chip (NoC) by modifying the structure of the data packets and reducing the number...
In this paper, we present some new crosstalk avoidance coding schemes devoted to on-chip busses. These schemes consist in encoding sequences of bits on each line of a bus transferring a packet in order to eliminate worst-case crosstalk patterns. They permit to improve the delay on the link at the cost of doubling the number of transmitted bits. The advantage of the presented solutions is that they...
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