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Sorting is a classic problem that has been studied for decades. From the beginning of computing, many Sorting algorithms have been investigated. Bubble sort is a very common and powerful sorting technique used in different applications. For high speed data processing, we need faster and efficient environment for any sorting algorithm. In this purpose, FPGA based hardware accelerators can show better...
The successive-approximation (SA) algorithm is traditionally used for low bandwidth applications because it requires n clock cycles or more to obtain n-bit resolution. However, the use of modern nanometer CMOS technologies and special design solutions overcome the speed limit, enabling conversion rates in the hundreds of MHz with very low power consumptions. This design uses the successive-approximation...
A method for experimental determination of the phase dependence of single-event sensitivity in high-speed A/MS circuits is presented. The technique ensures testing coverage of the complete data cycle and results in a correlation of errors to the data or clock cycle of the circuit. Designers can apply the information, along with knowledge of the circuit state at the time of errors, to make informed...
The work presented in this paper is aimed at designing an optimized convolutional interleaver for realtime application using Digital Signal Processor. Interleaving is a simple and effective means to improve the performance of an error correction scheme on a bursty channel. Convolutional interleaver is considered as one of the best option for researchers besides of block and helical interleaver. In...
Ternary Content Addressable Memories (CAMs) are widely used by high-speed routers to find matching routes in a routing table, because they enable the longest prefix matching operation to complete in a single clock cycle. However, they are costly and their power consumption is very high. In this paper, we identify two kinds of redundancy in the usage of TCAMs in IP route lookup, and then propose a...
This paper presents a new hardware implementation for boolean matrix inverters. A circuit capable of inverting a nonsingular N×N matrix in exactly N clock cycles is introduced, described, and tested in FPGA devices. This is an improvement over the fastest implementation reported to date, which computes the inverted matrix in 2N clock cycles on average or (N2+N)/2 clock cycles in the worst case. The...
A high-speed low-power self-calibrated pipeline ADC is presented. Gain error due to low-gain opamp used in multiplying DAC (MDAC) is corrected by the proposed foreground calibration technique. It adjusts the inter-stage gain by connecting a calibration capacitor into the MDAC positive feedback path. It only requires 168 clock cycles to complete the calibration without external precise references....
This paper presents the design and analysis high performance matrix filling for DNA sequence alignment accelerator using ASIC design flow. The objective of this paper is to design and analysis matrix module of DNA sequence alignment accelerator using clock cycle to get high performance. The scope of this paper is to optimize the DNA sequences alignment on the matrix filling module by implementing...
The main contribution of this paper is to present an efficient hardware algorithm for RSA encryption/decryption based on Montgomery multiplication. Modern FPGAs have a number of embedded DSP blocks (DSP48E1) and embedded memory blocks (BRAM). Our hardware algorithm supporting 2048-bit RSA encryption/decryption is designed to be implemented using one DSP48E1, one BRAM and few logic blocks (slices)...
A Field Programmable Gate Array (FPGA) is used to embed a circuit designed by users instantly. FPGAs can be used for implementing hardware algorithms. Most of FPGAs have Configurable Logic Blocks (CLBs) to implement combinational and sequential circuits and block RAMs to implement Random Access Memories (RAMs) and Read Only Memories (ROMs). Circuit design that minimizes the number of clock cycles...
We have introduced the Globally-Ratiochronous, Locally-Synchronous (GRLS) design paradigm, a design style based on rationally-related frequencies, with the objective to overcome the limitations of traditional multi-frequency systems by providing a flexibility close that of Globally-Asynchronous, Locally-Synchronous (GALS) systems but introducing performance penalties and overheads close to those of...
The Fast Fourier Transform (FFT) is a very important algorithm in signal processing, software defined radio and the most promising modulation technique i.e. Orthogonal Frequency Division Multiplexing (OFDM). This paper describes the design and implementation of a fully pipelined 64-point FFT engine in programmable logic. The FFT takes 16-bit fixed point complex numbers as input and after a known pipelined...
This work proposes a testable QCA (Quantum-Dot Cellular Automata) logic gate (UQCALG) realizing the universal functions. The design of UQCALG is based on the Coupled Majority Minority (CMVMIN) QCA structure with the target to reduce wire crossings as well as the number of clock cycles required to operate a QCA circuit. The characterization of defects in such design leads to synthesis of a test block,...
This study proposes a output loading effect insensitive and high precision clock synchronization (HPCS) circuit which can accept variable duty cycle clock signal. This HPCS is capable of synchronizing the external clock and the internal clock in 3 clock cycles. By using three innovative techniques, the proposed HPCS can also reduce the clock skew between the external clock and the internal clock in...
This work presents a novel bit-parallel systolic multiplier for the shifted dual basis of GF(2m). The shifted dual basis multiplication for all trinomials can be represented as the sum of two Hankel matrix-vector multiplications. The proposed multiplier architecture comprises one Hankel multiplier and one (2m-1)-bit adder. The algebraic encoding scheme based on linear cyclic codes is adopted to implement...
An equivalent optimized sub-pipelined architecture is proposed to implement the AES, every round including encryption and decryption needs one clock cycle. The SubBytes/InvSubBytes operation using composite field arithmetic in GF(24) and BlockRAMs respectively. In addition, an efficient key expansion which supports the output of 128 bits key per cycle and allows key changes every cycle is also presented...
The use of synthesizable reconfigurable IP cores has increasingly become a trend in System on Chip (SoC) designs because of their flexibility and powerful functionality. The market introduction of multi-featured platform FPGAs equipped with embedded memory and processor blocks has further expanded the possibility of utilizing dynamic reconfiguration to improve overall system adaptability to meet varying...
Connected component processing is a method used for segmenting an image into regions by means of grouping connected pixels of similar value. To do this, the current pixel value is compared to other connected pixel values, typically four or eight other values. Multiple read cycles would be required if these values are stored in a single bank memory. This paper presents an application of multiple-bank...
This paper presents a hardware implementation of a control algorithm for the log2(N, 0, p) switching fabric. This algorithm controls both connections and disconnections in the strict sense of a nonblocking switching fabric. The hardware implementation of this algorithm in Virtex5 circuits is described. The presented implementation has been optimized in order to minimize the time response of the controller...
The emerging H.264 SVC (Scalable Video Coding) standard specifies an encoder solution responsible for generating a multi-layer stream, which provides extra flexibility for modern multimedia applications. The increased data dependency among different layers demands a significant overall encoder performance. Aiming the use of an SVC solution in real-time applications we propose an optimized hardware...
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