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This paper analyzes high-speed source-synchronous network-on-chip data links in terms of yield loss due to delay variations. We show that statistical process variations can significantly reduce yield at high data rates and high bus widths. An on-chip delay calibration architecture for individual calibration of rise and fall delay times is proposed and analyzed on system level using Monte Carlo simulations...
Communication architecture design is a key issue of hardware/software co-design. This paper presents a novel architecture design method, called architecture generation and optimization method (AGOM) to assist embedded system designers to construct optimized on-chip communication architectures (OOCAs). The method outlines a new system design framework to achieve an application-specification architecture...
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