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Celem artykułu jest opisanie doświadczeń i wniosków płynących z zastosowania technik asynchronicznych w jakościowym badaniu podłużnym prowadzonym w trakcie pandemii COVID-19. Opracowanie ukazuje korzyści i ograniczenia oraz szanse i zagrożenia podejścia metodologicznego wykorzystującego wymianę asynchroniczną i dzienniczki. Perspektywa temporalna pozwoliła uchwycić dynamikę zmian związaną z pandemią,...
Embedded application environments require both high performance and low power. Architectures exploiting instruction-level parallelism (ILP) at compile time, such as very long instruction word (VLIW) and transport triggered architecture (TTA), may satisfy the requirements. They can be further enhanced by using asynchronous circuits to significantly reduce power consumption. As such, we are interested...
Over the past years, we have developed several parallel implementations of the MLFMA in two and three dimensions, for the broadband EM characterization of large structures. We have reviewed how the hierarchical partitioning can result into scalable algorithms. Asynchronous techniques allow for the simulation of problems with a large number of dielectric objects. Experiments indicate that large scale...
An 8-bit, 3-stage asynchronous gated ring oscillator (GRO) time-to-digital converter (TDC) is presented. It employs asynchronous techniques to achieve minimum GRO stages. This lead to about 40% to 70% gate count reduction compared to synchronous GRO-TDC. Count-missing, glitch, and unnecessary addition are eliminated. The uncorrupted noise shaping characteristic is obtained. The chip is implemented...
In this article are analyzed the message queues aiming to improve the message management, more precisely to reduce or eliminate the obsolete messages and, thus, reduce the costs for obtaining the solution. This thing allows the improvement of the performances of the ABT family techniques. Asynchronous techniques use some message processing routines. Those procedures process sequentially or in batches...
As technological advances make it possible to integrate an entire system on a single die, the designer of a system-on-chip (SoC) is confronted with increasing difficulties concerning complexity, reliability, energy and power consumption, and clock distribution. All those issues are aggravated by increasing parameters variability as a result of the same technological advances. This paper argues that...
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