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article

Performance characterization of video analytics workloads in heterogeneous edge infrastructures

Daniel Rivas, Francesc Guim, Jordà Polo, David Carrera

Concurrency and Computation: Practice and Experience > 35 > 14 > n/a - n/a

Powered by deep learning, video analytic applications process millions of camera feeds in real‐time to extract meaningful information from their surroundings. And this number grows by the minute. To avoid saturating the backhaul network and provide lower latencies, a distributed and heterogeneous edge cloud is postulated as a key enabler for widespread video analytics. This article provides a complete...

article

A 0.65-V, 500-MHz Integrated Dynamic and Static RAM for Error Tolerant Applications

Amit Kazimirsky, Adam Teman, Noa Edri, Alexander Fish

IEEE Transactions on Very Large Scale Integration (VLSI) Systems > 2017 > 25 > 9 > 2411 - 2418

The diminishing returns provided by voltage scaling have led to a recent paradigm shift toward so-called “approximate computing,” where computation accuracy is traded off for cost in error-tolerant applications. In this paper, a novel approach to achieving the power–performance–area versus data integrity tradeoff is proposed by integrating robust static memory cells and error-prone dynamic cells within...

article

GHEVC: An Efficient HEVC Decoder for Graphics Processing Units

Diego F. de Souza, Aleksandar Ilic, Nuno Roma, Leonel Sousa

IEEE Transactions on Multimedia > 2017 > 19 > 3 > 459 - 474

The high compression efficiency that is provided by the high efficiency video coding (HEVC) standard comes at the cost of a significant increase of the computational load at the decoder. Such an increased burden is a limiting factor to accomplish real-time decoding, specially for high definition video sequences (e.g., Ultra HD 4K). In this scenario, a highly parallel HEVC decoder for the state-of-the-art...

chapter

Analysis on scalability and energy efficiency of HEVC decoding using task-based programming model

Georgios Georgakarakos, Simon Holmbacka, Johan Lilius

2016 Conference on Design and Architectures for Signal and Image Processing (DASIP) > 34 - 41

2016 Conference on Design and Architectures for Signal and Image Processing (DASIP)

In this paper we evaluate the impact of task programming model in scalability and energy efficiency of dynamically parallel applications like HEVC decoding. We develop a task-based parallel HEVC decoding implementation supporting Tiles and Wavefront Parallel Processing. We measure and compare thread-based HEVC decoding against its alternative version supporting task-based parallelism. Results show...

chapter

Video Streaming to Mobile Handheld Devices: Challenges in Decoding, Adaptation, and Browsing

Chang Wen Chen, Houqiang Li

Lecture Notes in Computer Science > Multimedia Content Analysis and Mining > Invited Contributions > 42-51

Growing popularity and richer functionality of contemporary mobile handheld devices such as PDAs and smart phones have enabled emerging video streaming applications to these devices via various wireless networks. However, these handheld devices are significantly constrained by limited resources available to them for some sophisticated operations. Among these limitations, the available processing power...

chapter

CUDA Acceleration for AVS2 Loop Filtering

Songyi Li, Ronggang Wang, Kaili Yao

2016 IEEE Second International Conference on Multimedia Big Data (BigMM) > 246 - 250

2016 IEEE Second International Conference on Multimedia Big Data (BigMM)

Parallel computing platforms integrating CPU cores and mass of GPU accelerators have established in several application domains, obtaining remarkable time saving. In this way, video decoders can exploit a broader design space, to take full advantages of the hybrid GPU and CPU computing framework. Several novel contributions that aim at the exploitation of the maximum parallelism level in an AVS2 filtering...

article

Reconfigurable Interpolation Architecture for Multistandard Video Decoding

Gwo Giun Lee, Tzu-Chiang Tai, Wei-Chiao Yang, Chun-Fu Chen, more

Journal of Signal Processing Systems > 2016 > 84 > 2 > 251-264

Subpixel interpolation is an essential part to increase coding efficiency in many video compression standards. There arises the need to support the interpolation processes in multiple standards. In this paper, we propose a reconfigurable interpolation architecture for video decoding in MPEG-2, MPEG-4, and AVC/H.264. To reduce the hardware complexity and improve the operation efficiency, we analyze...

article

A Fast Algorithm-Based Cost-Effective and Hardware-Efficient Unified Architecture Design of 4 × 4, 8 × 8, 16 × 16, and 32 × 32 Inverse Core Transforms for HEVC

Chia-Wei Chang, Hao-Fan Hsu, Chih-Peng Fan, Chung-Bin Wu, more

Journal of Signal Processing Systems > 2016 > 82 > 1 > 69-89

In this study, a novel fast algorithm based hardware-sharing architecture for 4 × 4, 8 × 8, 16 × 16, and 32 × 32 inverse core transforms in high-efficiency video coding (HEVC) with a cost effective and highly hardware efficient design is developed. By using the symmetrical characteristics of the elements in inverse core transform matrices, the core transform matrix with symmetrical characteristics...

article

A video decoding optimization for heterogeneous dual-core platforms architecture

Yung-Sung Huang, Bin-Chang Chieu

Multimedia Tools and Applications > 2016 > 75 > 1 > 627-646

Digital signal processors (DSPs), with their powerful computing abilities, are commonly used for multimedia coding/decoding processes. Therefore, the SOC (System on Chip) industry integrates DSP with ARM (Advanced RISC Machine) for input/output processing, saving power, and building up a multi-core platform used in handheld devices. The computing ability of ARM has been substantially improved with...

article

An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding

Leibo Liu, Dong Wang, Min Zhu, Yansheng Wang, more

IEEE Transactions on Multimedia > 2015 > 17 > 10 > 1706 - 1720

A coarse-grained reconfigurable processing unit (RPU) consisting of $16 \times 16$ multi-functional processing elements (PEs) interconnected by an area-efficient line-switched mesh connect (LSMC) routing is implemented on a $5.4~\hbox{mm} \times 3.1~\hbox{mm}$ die in TSMC 65 nm LP1P8M CMOS technology. A hierarchical configuration context (HCC) organization scheme is proposed to reduce the implementation...

chapter

Robust video decoding by exploiting residual source redundancy

Lulu Sun, Shaoshuai Gao

2015 International Conference on Wireless Communications & Signal Processing (WCSP) > 1 - 5

2015 International Conference on Wireless Communications & Signal Processing (WCSP)

To achieve high compression efficiency, traditional video coding standards like H.264/AVC usually use entropy coding and prediction coding. As a result, a single channel error may lead to artifacts in decoding the following bitstream and even affect the following frames, which will deteriorate the video quality greatly. A robust video decoding method called the iterative verification decoding (IVD)...

chapter

Estimating the HEVC decoding energy using high-level video features

Christian Herglotz, Andre Kaup

2015 23rd European Signal Processing Conference (EUSIPCO) > 1591 - 1595

2015 23rd European Signal Processing Conference (EUSIPCO)

This paper shows how the decoding energy of HEVC software decoders can be estimated when using high-level features of a coded bit stream. The investigated features comprise number of frames, resolution, bitrate, QP, and encoder configuration, where the proposed model reaches an average estimation error of 10%. While establishing this model, we closely investigated the influence of these high-level...

article

Beyond pure quality: Progressive modes, region of interest coding, and real time video decoding for PDE-based image compression

Pascal Peter, Christian Schmaltz, Nicolas Mach, Markus Mainberger, more

Journal of Visual Communication and Image Representation > 2015 > 31 > Complete > 253-265

Compared to transform-based image compression methods such as JPEG2000, approaches based on partial-differential equations (PDEs) are in a proof-of-concept stage. Nevertheless, R-EED, a codec employing edge-enhancing anisotropic diffusion (EED) and rectangular subdivision, can surpass JPEG2000 quality-wise. However, today’s requirements for compression algorithms go beyond pure compression performance...

chapter

HEVC decoder optimization in low power configurable architecture for wireless devices

Vasileios Magoulianitis, Ioannis Katsavounidis

2015 IEEE 16th International Symposium on A World of Wireless, Mobile and Multimedia Networks (WoWMoM) > 1 - 6

2015 IEEE 16th International Symposium on "A World of Wireless, Mobile and Multimedia Networks" (WoWMoM)

High Efficiency Video Coding (HEVC) is the new video compression standard, reducing bitrates nearly at half compared to H.264, offering potentially significant power savings for wireless video transmission at the network interface. This reduction in bitrate is achieved by a series of computationally expensive algorithms, thus making imperative to optimize HEVC decoding in order to provide a low-power...

chapter

A model-based approach for architecture-independent video decoding

Christian Schenk, Sonja Maier, Uwe M. Borghoff

2015 International Conference on Collaboration Technologies and Systems (CTS) > 407 - 414

2015 International Conference on Collaboration Technologies and Systems (CTS)

Digital videos play an important role and are generally worth being preserved not only for historical reasons. In order to be able to play them, decoders are needed, which, however, as any kind of software are architecture-specific and can potentially not be executed on future hardware. To overcome this issue, we propose a multilevel approach that combines serialization standardization and model-based...

article

List Scheduling in Embedded Systems Under Memory Constraints

Paul-Antoine Arras, Didier Fuin, Emmanuel Jeannot, Arthur Stoutchinin, more

International Journal of Parallel Programming > 2015 > 43 > 6 > 1103-1128

Video decoding and image processing in embedded systems are subject to strong resource constraints, particularly in terms of memory. List-scheduling heuristics with static priorities (HEFT, SDC, etc.) being the oft-cited solutions due to both their good performance and their low complexity, we propose a method aimed at introducing the notion of memory into them. Moreover, we show that through adequate...

chapter

High-efficiency multiple 4×4 and 8×8 inverse transform design with a cost-effective unified architecture for multistandard video decoders

Chia-Wei Chang, Hao-Fan Hsu, Chih-Peng Fan

2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) > 507 - 510

2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

This study developed multiple-inverse transform-based fast algorithms and a hardware-sharing design for 4×4 and 8×8 inverse transforms in H.264/AVC, VC-1, HEVC, and AVS standards for 8×8 inverse discrete cosine transforms in MPEG-1/2/4 schemes. The 4×4 VP8 inverse transform was developed using cost-effective hardware suitable for multistandard video decoding applications. Matrix factorizations were...

chapter

Energy-efficient co-scheduling of receiving packets and decoding tasks on mobile video streaming terminals

Hongxing Guo, Keben Hu, Tao Xia

2014 IEEE International Conference on Multimedia and Expo Workshops (ICMEW) > 1 - 6

2014 IEEE International Conference on Multimedia and Expo Workshops (ICMEW)

An energy-efficient co-scheduling policy for packet receiving and video decoding tasks is proposed for a mobile terminal receiving video streaming packets from a access point(AP) in a WLAN. Through analyzing the interaction between the network interface card(NIC) and the CPU, a frame buffer between the NIC and the CPU is set to facilitate the cooperation of video packet receiving and video decoding...

article

Cloud-Assisted Smart Camera Networks for Energy-Efficient 3D Video Streaming

Zhangyu Guan, Tommaso Melodia

Computer > 2014 > 47 > 5 > 60 - 66

Despite current obstacles, smart camera networks that offload computationally intensive tasks to remote servers could allow energy-efficient 3D and multiview video encoding and delivery yet still ensure high-quality multiple-device video streaming.

article

Auxiliary stream for optimizing memory access of video decoders

ShaoLi Liu, Ling Li, YunJi Chen, WeiWu Hu

Science China Information Sciences > 2014 > 57 > 1 > 1-10

Due to the ever increasing resolution and frame rate of mainstream video sequences, memory access has become the main performance bottleneck of video decoding. To reduce the required off-chip memory, many decoders employ on-chip cache. However, they cannot distinguish whether a data block is reusable due to the lack of the information of undecoded Macro Blocks (MBs), thus often evicting reusable data...

INFONA - science communication portal

Search results

Performance characterization of video analytics workloads in heterogeneous edge infrastructures

A 0.65-V, 500-MHz Integrated Dynamic and Static RAM for Error Tolerant Applications

GHEVC: An Efficient HEVC Decoder for Graphics Processing Units

Analysis on scalability and energy efficiency of HEVC decoding using task-based programming model

Video Streaming to Mobile Handheld Devices: Challenges in Decoding, Adaptation, and Browsing

CUDA Acceleration for AVS2 Loop Filtering

Reconfigurable Interpolation Architecture for Multistandard Video Decoding

A Fast Algorithm-Based Cost-Effective and Hardware-Efficient Unified Architecture Design of 4 × 4, 8 × 8, 16 × 16, and 32 × 32 Inverse Core Transforms for HEVC

A video decoding optimization for heterogeneous dual-core platforms architecture

An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding

Robust video decoding by exploiting residual source redundancy

Estimating the HEVC decoding energy using high-level video features

Beyond pure quality: Progressive modes, region of interest coding, and real time video decoding for PDE-based image compression

HEVC decoder optimization in low power configurable architecture for wireless devices

A model-based approach for architecture-independent video decoding

List Scheduling in Embedded Systems Under Memory Constraints

High-efficiency multiple 4×4 and 8×8 inverse transform design with a cost-effective unified architecture for multistandard video decoders

Energy-efficient co-scheduling of receiving packets and decoding tasks on mobile video streaming terminals

Cloud-Assisted Smart Camera Networks for Energy-Efficient 3D Video Streaming

Auxiliary stream for optimizing memory access of video decoders

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