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A dynamic bias pre-amplifier based latch type comparator is designed in a 65nm CMOS process. Its performance is compared with the double-tail latch-type comparator fabricated on the same chip in terms of energy consumption, input referred noise and speed. Measurements demonstrate that the proposed dynamic bias pre-amplifier based comparator consumes 2.8 times less energy per comparator operation with...
This paper reports a power-efficient equalizing receiver designed for multi-data rate serial link applications. It includes a continuous-time linear equalizer (CTLE) and a halfrate 1-tap speculative decision feedback equalizer (DFE). The proposed StrongArm latch-based DFE adopts a novel non-50% duty-cycle clocking scheme to achieve 20% higher speed compared with the conventional 50% duty-cycle clocking...
Practical simulation and measurement methods based on impulse sensitivity functions to characterize the sampling aperture of clocked comparators are demonstrated on a 90 nm CMOS testchip. The results comparing a StrongARM latch and a CML latch suggest that the StrongARM latch has a narrower aperture of 23 ps but its aperture center is more sensitive to supply (65 ps/V). The CML latch has a higher...
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