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Items from 1 to 20 out of 470 results

article

A deep learning based latency aware predictive routing model for network‐on‐chip architectures

M. Venkata Sudhakar, P. Rahul Reddy, Usthulamuri Penchalaiah, P. Raghava Reddy

International Journal of Communication Systems > 36 > 17 > n/a - n/a

Network on Chip (NoC) is an evolving platform for communications related applications, which are executed on a single silicon chip. There are several routing models in NoC architectures, but the accuracy of these models is limited, and the existing models are degraded because of over and under fitting issues. This research introduces the new deep learning‐based latency aware predictive routing model...

article

A routing algorithm and a router architecture for 3D NoC

Somasundaram Kanagasabapathi, Chythanya Calicut

Computer Science > 2019 > Vol. 20 (3) > 369--383

In recent years, the enhancement of microchip technologies has enabled large scale Systems-on-Chip (SoC). Due to sharp increase in number of processing elements, SoC faces various challenges in design and testing. Network on Chip (NoC) is an alternative technology to overcome the challenges in SoC design and testing. NoC emerged as a key architecture that allows one to optimize the parameters like...

article

Application-aware Multi-Objective Routing based on Genetic Algorithm for 2D Network-on-Chip

A. Benmessaoud Gabis, P. Bomel, M. Sevaux

Microprocessors and Microsystems > 2018 > 61 > C > 135-153

This paper presents a technique using a genetic algorithm to compute an efficient routing for an application-specific NoC (Network-on-Chip). The main goal of this paper is to introduce multi-objective optimization techniques to address the NoC routing. Thus, Pareto optimization has been used to determine non-dominated solutions according to two fixed objectives: (i) avoiding the reuse of same links...

article

A highly efficient dynamic router for application-oriented network on chip

Nan Su, Huaxi Gu, Kun Wang, Xiaoshan Yu, more

The Journal of Supercomputing > 2018 > 74 > 7 > 2905-2915

With the number of processor cores increasing in chip multiprocessors, the network on chip becomes a reliable structure with its perfect parallel communication performance. The traditional static router suffers a bad performance because of low buffer utilization for application-oriented network on chip. In this paper, a dynamic router which can take into account the unbalanced traffic for application-oriented...

article

An Efficient FPGA-Based Parallel Phase Unwrapping Hardware Architecture

Huan-Yuan Chen, Shu-Hao Hsu, Wen-Jyi Hwang, Chau-Jern Cheng

IEEE Transactions on Computational Imaging > 2017 > 3 > 4 > 996 - 1007

This paper presents a novel phase unwrapping hardware architecture for imaging applications. The architecture is a hardware implementation of a path-independent noniterative discrete cosine transform (DCT) based minimum mean square algorithm for accurate and fast phase unwrapping. The implementation is based on field programmable gate array. The architecture is able to exploit the parallelism among...

article

Energy-Aware and Reliability-Aware Mapping for NoC-Based Architectures

Naresh Kumar Reddy Beechu, Vasantha Moodabettu Harishchandra, Nithin Kumar Yernad Balachandra

Wireless Personal Communications > 2018 > 100 > 2 > 213-225

Extensive research has been conducted on task scheduling and mapping on a multi-processor system on chip. The mapping strategy on a network on chip (NoC) has a huge effect on the communication energy and performance. This paper proposes an efficient core mapping for NoC-based architectures. Which focus on energy- aware and reliability-aware mapping issues for NoC-based architectures and considers...

chapter

An analytical model for segmented bus enhanced network on chip

Hossein Bastan, Mohammad Ali Montazeri, Amin Ghalami Osgouei, Amir Khorsandi, more

2017 7th International Conference on Computer and Knowledge Engineering (ICCKE) > 72 - 76

2017 7th International Conference on Computer and Knowledge Engineering (ICCKE)

Several analytical models have been proposed for wormhole-routing network on chip while there is few analytical model for fully adaptive routing. To the best of our knowledge, there is not analytical model for segmented bus. In this paper, a new analytical delay model presented for hybrid Bus-NoC. First we present an analytical model for segmented bus, then by improving the mesh analytical model,...

chapter

Relocation-aware communication network for circuits on Xilinx FPGAs

Adewale Adetomi, Godwin Enemali, Tughrul Arslan

2017 27th International Conference on Field Programmable Logic and Applications (FPL) > 1 - 7

2017 27th International Conference on Field Programmable Logic and Applications (FPL)

The parallelism of hardware and the dynamic reconfigurability of FPGAs enable multiple hardware tasks to run concurrently, and also time-share resources by being swapped in and out of the device during runtime. More than ever before, these capabilities are being employed in systems with high-reliability requirements. To improve reliability, a method often used is circuit relocation. However, the static...

chapter

Exploiting the Dynamic Partial Reconfiguration on NoC-Based FPGA

Amr Hassan, Hassan Mostafa, Hossam A. H. Fahmy, Yehea Ismail

2017 New Generation of CAS (NGCAS) > 277 - 280

2017 New Generation of CAS (NGCAS)

Dynamic Partial Reconfiguration (DPR) of SRAM-based Field Programmable Gate Arrays (FPGAs) becomes a demanding feature by many applications for its ability to add more flexibility over runtime phase. Recently, implementation designs which utilize DPR are easier than before. However, techniques that FPGAs use to perform DPR (like ICAP and JTAG) encounter a performance bottleneck; only one DPR is allowed...

chapter

Sthira: A Formal Approach to Minimize Voltage Guardbands under Variation in Networks-on-Chip for Energy Efficiency

Raghavendra Pradyumna Pothukuchi, Amin Ansari, Bhargava Gopireddy, Josep Torrellas

2017 26th International Conference on Parallel Architectures and Compilation Techniques (PACT) > 260 - 272

2017 26th International Conference on Parallel Architectures and Compilation Techniques (PACT)

Networks-on-Chip (NoCs) in chip multiprocessors are prone to within-die process variation as they span the whole chip. To tolerate variation, their voltages (Vdd) carry over-provisioned guardbands. As a result, prior work has proposed to save energy by operating at reduced Vdd while occasionally suffering and fixing errors. Unfortunately, these proposals use heuristic controller designs that provide...

chapter

A time multiplexed network architecture for large-scale neuromorphic computing

Rezwan A Rasul, Pedram Teimouri, Mike Shuo-Wei Chen

2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS) > 1216 - 1219

2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)

Emerging trend in neuromorphic implementation moves towards large-scale neuron array that processes large amount of input data. It presents a grand challenge in communication between neurons due to large number of connections, or synapses, which can be in the order of millions, leading to large power consumption, processing time and many physical wires. In this work, we propose a communication protocol...

article

A high fault coverage test approach for communication channels in network on chip

Babak Aghaei

Microelectronics Reliability > 2017 > 75 > C > 178-186

This paper proposes a new high fault coverage test approach for short faults in Network on Chip communication channels. The proposed approach consists of a built in self-test as well as a Packet/flit Comparing Module (PCM) embedded in the network adapter and a router, respectively. The approach is mainly characterized by the fact that, the detection, location, and routing table updating processes...

article

Tunable optical delay line for optical time-division multiplexer

Zhihua Yu, Qi Zhang, Hong Wang, Jingjing Zhang, more

Optics Communications > 2017 > 395 > C > 217-220

A novel three-stage all-pass filter (APF) is proposed as a tunable optical delay line to construct an optical time division multiplexer (OTDM), with which, we can get ultrahigh bit rates with several low-speed channels. The proposed design mitigates the deleterious effects of group delay dispersion and provides wide bandwidth with small ripples and continuously tunable long delays achieved with small...

article

Improved Performance of Error Controlling Codes Using Pass Transistor Logic

M. Chennakesavulu, T. Jayachandra Prasad, V. Sumalatha

Circuits, Systems, and Signal Processing > 2018 > 37 > 3 > 1145-1161

System-on-ship (SoC) design in the nanoelectronics era brings us not only many opportunities but also several challenges like synchronization, process uncertainty, global interconnecting delay, high scalability, and reliability. Network on Chip (NoC) could be a communication subsystem and it is rising as a revolutionary design methodology to solve the problems associated with SoC designing. Reliability...

chapter

Novel 3D-printing enabled antenna design for future wireless intra-chip interconnect

Junqiang Wu, Hao Xin

2017 IEEE International Symposium on Antennas and Propagation & USNC/URSI National Radio Science Meeting > 1237 - 1238

2017 IEEE International Symposium on Antennas and Propagation & USNC/URSI National Radio Science Meeting

A novel antenna design that is enabled by 3D printing technology for future wireless intra-chip communications is proposed in this work. Vertical quarter-wavelength monopoles are used for intra-chip communication, which avoids substrate-caused low antenna radiation efficiency. The monopoles are surrounded by specially-designed dielectric distribution. This additional design degree of freedom allowed...

chapter

Pipelined chipper based noc for performance enhancement

U. Sivaranjani, D. Muralidharan, R. Muthaiah

2017 International Conference on Networks & Advances in Computational Technologies (NetACT) > 95 - 98

2017 International Conference on Networks & Advances in Computational Technologies (NetACT)

Network on chip (Noc) is a neoteric technique, which is used to interconnect the nodes present in between the system on chip (Soc). In network on chip, routing is the important process to select the more appropriate and better path among the available path. In normal routing technique, the throughput and performance is moderate in order to get one output packet. To improve the throughput and performance...

article

The cost-effective fault detection and fault location approach for communication channels in NoC

Babak Aghaei, Kambiz Badie, Ahmad Khademzadeh, Midia Reshadi

The Journal of Supercomputing > 2017 > 73 > 11 > 5034-5052

In the current paper, we propose a new online search, fault detection, and fault location approach for short faults in network on chip communication channels. The approach proposed consists of a built-in self-test as well as a packet/flit comparings module embedded in the network adapter and a router, respectively. The approach is mainly characterized by the fact that, firstly, the diagnosis and location...

article

A New BIST-based Test Approach with the Fault Location Capability for Communication Channels in Network-on-Chip

Babak Aghaei, Ahmad Khademzadeh, Midia Reshadi, Kambiz Badie

Journal of Electronic Testing > 2017 > 33 > 4 > 501-513

In this paper, a new BIST based test approach to detecting short faults on the communication channels data links in network-on-chip is proposed. The rationale underlying the novelty of the proposed approach is that it is capable of locating the faulty channels while simultaneously performing the testing as well as updating the Routing Tables (RT) in which irregular Mesh-based and fault tolerant NoCs...

article

Efficient task spawning for shared memory and message passing in many-core architectures

Aurang Zaib, Thomas Wild, Andreas Herkersdorf, Jan Heisswolf, more

Journal of Systems Architecture > 2017 > 77 > C > 72-82

Modern many-core systems consist of large number of processing cores and introduce more and more parallelism. The (PGAS) programming model is a popular approach for exploiting this parallelism of architectures while offering flexibility of both shared memory and message passing paradigms. On the architecture design front, (NoCs) have become an integral part of the communication infrastructure due...

chapter

Activation of secure zones in many-core systems with dynamic rerouting

Luciano L. Caimi, Vinicius Fochi, Eduardo Wachter, Daniel Munhoz, more

2017 IEEE International Symposium on Circuits and Systems (ISCAS) > 1 - 4

2017 IEEE International Symposium on Circuits and Systems (ISCAS)

Many-core architectures provide massive parallelism and high performance to the users. They also introduce key challenges regarding security. The main threat rises from the resource sharing. Adoption of firewalls, encryption mechanisms and resource isolation (processor or memory) are common strategies to treat the security threats. The two first strategies present high hardware cost, while the resource...

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NETWORK ON CHIP (470)
NETWORK-ON-CHIP (199)
ROUTING (120)
SYSTEM-ON-A-CHIP (73)
NOC (66)
COMPUTER ARCHITECTURE (65)
TOPOLOGY (60)
NETWORK ROUTING (56)
NETWORK TOPOLOGY (54)
SWITCHES (47)
ALGORITHM DESIGN AND ANALYSIS (43)
FIELD PROGRAMMABLE GATE ARRAYS (41)
SYSTEM-ON-CHIP (38)
THROUGHPUT (38)
SYSTEM ON CHIP (35)
HARDWARE (33)
CLOCKS (32)
INTEGRATED CIRCUIT INTERCONNECTIONS (32)
DELAY (30)
FPGA (28)
INTEGRATED CIRCUIT DESIGN (28)
BANDWIDTH (25)
SYSTEM RECOVERY (25)
MULTIPROCESSING SYSTEMS (24)
PORTS (COMPUTERS) (24)
PROGRAM PROCESSORS (24)
IP NETWORKS (23)
ENERGY CONSUMPTION (22)
FAULT TOLERANCE (22)
MAGNETIC CORES (22)
SYNCHRONIZATION (22)
REGISTERS (21)
ROUTER (20)
POWER DEMAND (19)
MICROPROCESSOR CHIPS (18)
MULTIPROCESSOR INTERCONNECTION NETWORKS (18)
OPTIMIZATION (18)
RESOURCE MANAGEMENT (18)
LOGIC DESIGN (17)
QUALITY OF SERVICE (17)
ROUTING ALGORITHM (17)
POWER CONSUMPTION (16)
RELIABILITY (16)
DECODING (14)
EMBEDDED SYSTEMS (14)
RECONFIGURABLE ARCHITECTURES (14)
SCHEDULING (14)
MAPPING (13)
PROTOCOLS (13)
ROUTING PROTOCOLS (13)
WIRES (13)
TILES (12)
ANALYTICAL MODELS (11)
BUFFER STORAGE (11)
DATA MINING (11)
ENCODING (11)
FAULT TOLERANT SYSTEMS (11)
LOW POWER (11)
LOW-POWER ELECTRONICS (11)
NOC ARCHITECTURE (11)
CHIP MULTIPROCESSOR (10)
COMPUTATIONAL MODELING (10)
HEURISTIC ALGORITHMS (10)
INSTRUCTION SETS (10)
INTERCONNECTION NETWORK (10)
MULTICORE PROCESSING (10)
PERFORMANCE EVALUATION (10)
POWER DISSIPATION (10)
SOC (10)
TIMING (10)
DELAYS (9)
LOGIC GATES (9)
MATHEMATICAL MODEL (9)
MESH (9)
MESH NETWORKS (9)
MPSOC (9)
RECEIVERS (9)
SCALABILITY (9)
VIRTUAL CHANNEL (9)
ADAPTIVE ROUTING (8)
ARCHITECTURE (8)
CIRCUIT FAULTS (8)
COMPLEXITY THEORY (8)
FLOW CONTROL (8)
INTEGRATED CIRCUIT MODELING (8)
LATENCY (8)
NETWORK INTERFACES (8)
PIPELINES (8)
SIECI WEWNĄTRZUKŁADOWE (8)
SIMULATION (8)
TELECOMMUNICATION NETWORK ROUTING (8)
CHIP MULTIPROCESSORS (7)
CMOS INTEGRATED CIRCUITS (7)
GENETIC ALGORITHM (7)
MICROPROCESSORS (7)
MULTIPROCESSOR INTERCONNECTION (7)
NETWORK INTERFACE (7)
NICKEL (7)
NOC DESIGN (7)
ON-CHIP COMMUNICATION (7)
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Search results

A deep learning based latency aware predictive routing model for network‐on‐chip architectures

A routing algorithm and a router architecture for 3D NoC

Application-aware Multi-Objective Routing based on Genetic Algorithm for 2D Network-on-Chip

A highly efficient dynamic router for application-oriented network on chip

An Efficient FPGA-Based Parallel Phase Unwrapping Hardware Architecture

Energy-Aware and Reliability-Aware Mapping for NoC-Based Architectures

An analytical model for segmented bus enhanced network on chip

Relocation-aware communication network for circuits on Xilinx FPGAs

Exploiting the Dynamic Partial Reconfiguration on NoC-Based FPGA

Sthira: A Formal Approach to Minimize Voltage Guardbands under Variation in Networks-on-Chip for Energy Efficiency

A time multiplexed network architecture for large-scale neuromorphic computing

A high fault coverage test approach for communication channels in network on chip

Tunable optical delay line for optical time-division multiplexer

Improved Performance of Error Controlling Codes Using Pass Transistor Logic

Novel 3D-printing enabled antenna design for future wireless intra-chip interconnect

Pipelined chipper based noc for performance enhancement

The cost-effective fault detection and fault location approach for communication channels in NoC

A New BIST-based Test Approach with the Fault Location Capability for Communication Channels in Network-on-Chip

Efficient task spawning for shared memory and message passing in many-core architectures

Activation of secure zones in many-core systems with dynamic rerouting

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