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Items from 1 to 12 out of 12 results

article

Dynamic voltage frequency scaling-aware refresh management for 3D DRAM over processor architecture

J. Lim, H. Kim, H. Oh, S. Kang

Electronics Letters > 2017 > 53 > 14 > 910 - 912

Three-dimensional integrated systems that combine large-capacity dynamic random access memory (DRAM) with high-performance processors represent a promising solution to implementing high-performance computing. However, in such configurations stacked DRAM cells will inevitably be exposed to high temperatures generated by the processor, thereby necessitating DRAMs with high refresh rates driven by embedded...

article

Controller Architecture for Low-Power, Low-Latency DRAM With Built-in Cache

Zhi-Yong Liu, Hsiu-Chuan Shih, Bing-Yang Lin, Cheng-Wen Wu

IEEE Design & Test > 2017 > 34 > 2 > 69 - 78

Memory wall is a critical issue for many today’s electronic systems. Tiered latency DRAM with asymmetric bit lines was proposed to optimize the power and latency. This paper proposes a controller architecture for the tiered latency DRAM in which the small array is operated like a cache. —Jin-Fu Li, National Central University

chapter

A reconfigurable near-data systolic array accelerator for the three-dimensional DRAM systems

Shu-Yen Lin, Jin-Yi Lin, Cheng-Hung Lin

2016 IEEE 5th Global Conference on Consumer Electronics > 1 - 2

2016 IEEE 5th Global Conference on Consumer Electronics

In this work, we propose a reconfigurable near-data systolic array accelerator (NDSAA) for the 3D DRAM systems. The NDSAA supports the iterative operations for different applications, and the data movement between the processor core and the 3D DRAM is reduced. In our experiments, the 3D DRAM stacking the NDSAA reduces the latency by 51% ∼ 70% compared to the one stacking the general bi-directional...

chapter

Impact of local stress in 3D stacking process on memory retention characteristics in thinned DRAM chip

S. Tanikawa, H. Kino, T. Fukushima, K-W. Lee, more

2016 IEEE International Reliability Physics Symposium (IRPS) > 6B-1-1 - 6B-1-6

2016 IEEE International Reliability Physics Symposium (IRPS)

The effect of local stresses on memory retention characteristics has been characterized in detail. A retention time of memory cells in a DRAM chip with 200-μm thick was largely changed after under-fill shrinkage with Cu/Sn bumps. Meanwhile, after thinned down to 40-μm thick, the retention time of memory cell was not significantly changed in the whole area even with Cu/Sn bumps due to decreased stress...

article

Configurable Cubical Redundancy Schemes for Channel-Based 3-D DRAM Yield Improvement

Bing-Yang Lin, Wan-Ting Chiang, Cheng-Wen Wu, Mincent Lee, more

IEEE Design & Test > 2016 > 33 > 2 > 30 - 39

Three-dimensional stacked memory stacking logic and memory dies are one of the most promising 3-D integration applications. This paper proposes two memory redundancy schemes to improve the yield of channelbased 3-D stacked DRAM by sharing spare memory across dies and satisfying channel constraints at the same time. The proposed schemes achieve much higher yield with very small area overhead than other...

chapter

Analysis of asymmetric 3D DRAM architecture in combination with L2 cache size reduction

Alex Schoenberger, Klaus Hofmann

2015 International Conference on High Performance Computing & Simulation (HPCS) > 123 - 128

2015 International Conference on High Performance Computing & Simulation (HPCS)

Memory is a heterogeneous complex in modern systems. Access time and bandwidth improvement of DRAM using die-stacking technology can only be evaluated by interacting with hardware components like underlying cache, CPU and software components like executed application and processed input. In this work we analyze encoding and decoding processes of JPEG2000 algorithm execution on MIPS I core for different...

article

Logic-DRAM Co-Design to Exploit the Efficient Repair Technique for Stacked DRAM

Minjie Lv, Hongbin Sun, Qiwei Ren, Bing Yu, more

IEEE Transactions on Circuits and Systems I: Regular Papers > 2015 > 62 > 5 > 1362 - 1371

Three-dimensional (3D) integration is promising to provide dramatic performance and energy efficiency improvement to 3D logic-DRAM integrated computing system, but also poses significant challenge to the yield. To address this challenge, this paper explores a way to leverage logic-DRAM co-design to reactivate unused spares and thereby enable the cost-efficient technique to repair 3D integration-induced...

chapter

Design, packaging, and architectural policy co-optimization for DC power integrity in 3D DRAM

Yarui Peng, Bon Woong Ku, Younsik Park, Kwang-Il Park, more

2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC) > 1 - 6

2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

3D DRAM is the next-generation memory system targeting high bandwidth, low power, and small form factor. This paper presents a cross-domain CAD/architectural platform that addresses DC power noise issues in 3D DRAM targeting stacked DDR3, Wide I/O, and hybrid memory cube technologies. Our design and analysis include both individual DRAM dies and a host logic die that communicates with them in the...

chapter

Enabling portable energy efficiency with memory accelerated library

Qi Guo, Tze-Meng Low, Nikolaos Alachiotis, Berkin Akin, more

2015 48th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) > 750 - 761

2015 48th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

Over the last decade, the looming power wall has spurred a flurry of interest in developing heterogeneous systems with hardware accelerators. The questions, then, are what and how accelerators should be designed, and what software support is required. Our accelerator design approach stems from the observation that many efficient and portable software implementations rely on high performance software...

chapter

Impacts of Cu contamination in 3D integration process on memory retention characteristics in thinned DRAM chip

Kangwook Lee, Seiya Tanikawa, Hideki Naganuma, Jichel Bea, more

2014 IEEE International Reliability Physics Symposium > 3E.4.1 - 3E.4.6

2014 IEEE International Reliability Physics Symposium (IRPS)

The influences of Cu contamination on 3D DRAM memory cell retention are characterized for Cu migration from the ground backside surface of a chip and Cu filled TSVs. The DRAM cell retention characteristics in chips thinned to 50-µm thickness then CMP polished are dramatically degraded, regardless of the well structure, after intentional Cu diffusion from the grinded backside surface at 300°C, 30 min...

chapter

Impact of 3-D integration process on memory retention characteristics in thinned DRAM chip for 3-D memory

K-W Lee, S. Tanikawa, M. Murugesan, H. Naganuma, more

2013 IEEE International 3D Systems Integration Conference (3DIC) > 1 - 4

2013 IEEE International 3D Systems Integration Conference (3DIC)

The Young's modulus (E) of Si substrate begins to noticeably decrease below 50-μm thickness. The Young's modulus in 30-μm thick Si substrate decreased by approximately 30% compared to the modulus of 50-μm thickness. In 30-μm thick Si substrate, the lattice structure of Si substrate is highly distorted. Large distortion of the lattice structure induces the Young's modulus reduction, consequently weakens...

chapter

Improving VLIW Processor Performance Using Three-Dimensional (3D) DRAM Stacking

Yangyang Pan, Tong Zhang

2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors > 38 - 45

2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors

This work studies the potential of using emerging 3D integration to improve embedded VLIW computing system. We focus on the 3D integration of one VLIW processor die with multiple high-capacity DRAM dies. Our proposed memory architecture employs 3D stacking technology to bond one die containing several processing clusters to multiple DRAM dies for a primary memory. The 3D technology also enables wide...

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Keywords

3D DRAM (12)
RANDOM ACCESS MEMORY (6)
THREE-DIMENSIONAL DISPLAYS (4)
DRAM CHIPS (3)
RETENTION TIME (3)
STACKING (3)
ARRAYS (2)
COMPUTER ARCHITECTURE (2)
HARDWARE (2)
MAINTENANCE ENGINEERING (2)
MICROPROCESSORS (2)
REDUNDANCY (2)
2D SRAM L2 CACHE (1)
3D DRAM L2 CACHE (1)
3D DRAM STACKING (1)
3D INTEGRATION (1)
ACCELERATION (1)
ACCELERATOR (1)
ALGORITHM DESIGN AND ANALYSIS (1)
ARCHITECTURAL POLICY (1)
BENCHMARK TESTING (1)
BIDIRECTIONAL CONTROL (1)
BUILT-IN CACHE DRAM (BC-DRAM) (1)
BUILT-IN SELF-REPAIR (BISR) (1)
BUILT-IN SELF-TEST (1)
BUILT-IN SELF-TEST (BIST) (1)
CACHE STORAGE (1)
CAPACITANCE-TIME (C-T) (1)
CHARGE CARRIER LIFETIME (1)
CIRCUIT FAULTS (1)
CONFERENCES (1)
CU DIFFUSION (1)
CU TSV (1)
CU/SN BUMP (1)
DELAYS (1)
DESIGN (1)
DIGITAL SIGNAL PROCESSING (1)
DRAM (1)
DRAM CONTROLLER (1)
DSP (1)
DYNAMIC RANDOM ACCESS MEMORY (1)
DYNAMIC VOLTAGE FREQUENCY SCALING-AWARE REFRESH MANAGEMENT (1)
EMBEDDED TEMPERATURE SENSORS (1)
EMBEDDED VLIW COMPUTING SYSTEM (1)
ENERGY EFFICIENCY (1)
FUSES (1)
HIGH-PERFORMANCE PROCESSORS (1)
INSTRUCTION SETS (1)
INTEGRATED CIRCUITS (1)
IR DROP (1)
JPEG2000 (1)
L2 CACHE (1)
LIBRARIES (1)
LIBRARY (1)
LOCALITY PRINCIPLE (1)
LOW-LATENCY BUSES (1)
LOW-POWER ELECTRONICS (1)
LOW-POWER TECHNIQUES (1)
MECHANICAL STRENGTH (1)
MECHANICAL STRESS (1)
MEMORY ARCHITECTURE (1)
MEMORY HIERARCHY (1)
MEMORY REPAIR (1)
MEMORY TESTING (1)
MOS CAPACITOR (1)
MULTIPROCESSING SYSTEMS (1)
NEAR-DATA PROCESSING (1)
PACKAGING (1)
PARALLEL ARCHITECTURES (1)
PARALLEL MACHINES (1)
PROCESSOR ARCHITECTURE (1)
REDUNDANCY ANALYSIS (RA) (1)
REDUNDANCY REPAIR (1)
REFRESH RATES (1)
SEMICONDUCTOR DEVICE MEASUREMENT (1)
SI YOUNG'S MODULUS (1)
SILICON (1)
SOFTWARE (1)
SRAM CHIPS (1)
STRESS (1)
SYSTOLIC ARRAY (1)
TEMPERATURE DISTRIBUTION (1)
TEMPERATURE SENSORS (1)
THERMAL DISTRIBUTION (1)
THERMALLY AWARE REFRESH-CONTROL METHOD (1)
THREE DIMENSIONAL DISPLAYS (1)
THREE-DIMENSIONAL INTEGRATED SYSTEMS (1)
TIERED LATENCY DRAM (TL-DRAM) (1)
TRANSISTORS (1)
VLIW (1)
YIELD (1)
YIELD IMPROVEMENT (1)
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