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The opamp in the first integrator of a high resolution single-bit continuous-time modulator has stringent slew rate requirements, which increases power dissipation. We introduce the “assisted opamp” integrator, which is a way of achieving low distortion operation with low power consumption. We present circuit implementations of our technique for single-bit modulators using NRZ and switched-capacitor-resistor...
For the first time, a scalable load balanced Birkhoff-von Neumann TDM switch IC with SERDES interface circuits for high speed networking applications was implemented. Any NtimesN Birkhoff-von Neumann TDM switch could be constructed recursively from the designed TDM switch IC to achieve switching capacity of hundred gigabits per second or higher. The TDM switch IC contained a digital 8times8 TDM switch...
A novel multi-band low noise amplifier (LNA) that allows simultaneous reception of signals from several wireless standards is designed and implemented using a 0.18-mum CMOS technology. The circuit topology consists of a 3-stage wideband LNA and 2 notch filters. The designed LNA can provide concurrent three bands over 0.935~5.825 GHz with measured gain (S21) of 15~24 dB, input reflection ratio (S11)...
This paper presents the architecture and design of current-mode phase-locked loops. The proposed current-mode PLLs differ from conventional voltage-mode PLLs by replacing their RC loop filter with a RL loop filter, eliminating the need for area-consuming capacitors. The large inductance of the current-mode loop filter is obtained from CMOS active inductors, taking the advantage of their large and...
A 0.18mum CMOS 2.4GHz LNA (low noise amplifier) with digitally switchable capacitance has been designed to investigate its ability to compensate for performance variation across worst case process conditions. The effects of transistor model and passive component variation are first simulated to quantify the range of performance uncertainty. The use of various methods of switchable capacitance is then...
Employing multiple supply voltages (multi-VDD) is attractive for reducing the power consumption without sacrificing the speed of an integrated circuit (IC). In order to transfer signals among the circuits operating at different voltage levels specialized voltage interface circuits are required. Two novel multi-threshold voltage (multi-Vth) level converters are proposed in this paper. The proposed...
A fully integrated, low-cost (area), low-power, high-gain, differential optical receiver analog front-end (AFE), including transimpedance amplifier (TIA), limiting amplifier (LA), DC-offset cancellation feedback and output-buffer is designed in TSMC 0.18μm CMOS technology. The optimized TIA has a regulated cascode (RGC) topology, with 5.9mW power-dissipation, 48 dBΩ gain, 8.46GHz bandwidth. The proposed...
This paper presents the design of a 12 Gbps multi-lane 231 - 1 pseudo-random binary sequence (PRBS) generator in 0.18 mum TSMC process. The design incorporates a traditional CMOS latch optimized to operate at frequencies close to the ft of the process. In order to operate at frequencies higher than the limit imposed by the ft of the PMOS devices, the PRBS uses current-mode logic (CML) multiplexers...
Design and verification of a low-voltage, low-power, and extremely small area successive approximation registered analog-to-digital converter (SARADC) for sensor network applications are presented. The 8-bit SARADC employed a capacitor-based hybrid digital-to-analog converter and a simplified digital control block to achieve low power consumption and small area and a charge pumped switch to reduce...
The implementation of a 0.18μm CMOS 2.1GHz sub-sampling receiver front end with fully integrated fourth-and second- order Q-enhanced LC filters is described. The use of an integrated fourth-order filter allows the amount of noise aliasing due to sub-sampling to be reduced and the bandwidth and roll-off factor to be independently controlled. When tuned to a high effective quality factor of 210, the...
For recording of neural signals from large population of neurons, stringent constraints are imposed on the design of neural amplifiers. We have designed neural amplifier in FD-SOI technology in order to achieve lower power consumption, smaller area, and better noise efficiency factor compared to the standard bulk processes. A symmetric pseudo resistor was realized with resistances on the order of...
A low power ultra-wideband (UWB) common-gate low noise amplifier (CGLNA) for IEEE 802.15.3a is presented. In order to save the power consumption, a current-reuse technology is used. For extending the bandwidth, the proposed circuit uses and the stagger tuning technique of two stacked stages with different resonant frequencies. The circuit is simulated with TSMC 0.18 mum mixed signal/RF CMOS process...
Regular gate-driven regulated-cascode structure fails to operate with very-low supply voltages. On the other hand, body-driven configuration suffers from limited speed due to limited effective transconductance. In this letter, body-driven gain-boosting amplifier has been employed for a regular gate-driven folded-cascode amplifier to enhance its voltage gain without any limitation on its minimum required...
In this paper, the matched performance of a dual band PIFA antenna is reported. The transducer power gain of the matched antenna is optimized over the popular commercial wireless communication bands of 824-960 MHz and 1710-1990 MHz using only one matching network. The antenna matching network was designed using the simplified real frequency technique and it was realized employing 0.18μm Si-processing...
A 2.5Gb/s burst-mode limiting amplifier for gigabit passive optical networks (GPON) is presented in this paper. A multistage architecture with a feedforward automatic threshold control (ATC) circuit is used for quick response. A response time of 5ns and sensitivity of 4 mVpp1 is achieved by introducing a modified ATC circuit and a modified amplified stage with active feedback and negative Miller capacitance...
In recent years, continuous research efforts have been concentrating in increasing ΣΔ modulators operating frequency, while still reducing their power consumption. Indeed, when the ΣΔ modulator figure of merit (FoM) is less than 1 pJ/conversion, the decimation filter power consumption becomes a critical parameter. This paper presents a low power sin3 FIR filter for ΣΔ modulators. The proposed filter...
A low power CMOS voltage reference circuit was designed and implemented by TSMC 0.18-mum CMOS process. The voltage reference circuit uses the VGS difference between two MOSFETs operating in the weak-inversion region to generate the voltage with positive temperature coefficient. The reference voltage can be obtained by combining the weighted VGS difference with weak-inversion VGS voltage, which has...
In this paper, capabilities of switched-current (SI) circuits are utilized to design a high-speed A/D converter. New methods to improve the performance of the SI circuits are introduced. An 8-bit 300MS/s pipeline ADC is design in 0.18mum CMOS technology and an ENOB of 7.3b is obtained from simulations. The ADC consumes 40mW from a 1.8V supply.
This paper presents a low-voltage, reduced-area CMOS bandgap reference (BGR) circuit for low-power applications. Significant area reduction is achieved by utilizing a resistive T-network in combination with layout-efficient opamp compensation. A complete analysis, including the dual-loop stability, reveals several tradeoffs between area, loop-gain, stability and offset sensitivity. Based on this analysis,...
Context-based adaptive 2D-VLC (CA-2D-VLC) is adopted by AVS. In this paper, we present an area-efficient VLSI implementation of CA-2D-VLC decoder. Data compression storage (DCS) method is proposed in memory optimization for VLC tables and a reduction of 30% in on-chip memory cost is achieved. Furthermore, an Exp-Golomb decoder is developed with codeword segmentation decoding (CSD) method, which saves...
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