The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Promoted by the component miniaturization trend, three-dimensional integration appears as a promising option for implementation of the next generation of integrated circuits. In this context, copper is still an interesting material to be integrated to vertical interconnexion through direct metal-metal bonding processes. However, it was already reported that voiding phenomena occur in bonded copper...
Metal films can be used as bonding layers at wafer-level in manufacturing processes for device assembly as well as just for electrical integration of different components. One has to distinguish between two categories of processes: metal thermo-compression bonding on one side, and bonding with formation of a eutectic or an intermetallic alloy layer. The different process principles determine also...
For the first time we demonstrate the CMOS integration of undoped fully-depleted Ultra Thin Body and BOX devices (UTB2) with (110)/(100) substrate crystal orientation for pFET and nFET respectively. For this, we used an original 3D-folded Bulk+/Silicon-On-Nothing (SON) process on DSB substrate. Resulting multi-surface orientations devices are studied.
Due mainly to the thermal budget of CMOS devices, bonding techniques compatible with CMOS processing are limited to direct oxide bonding, metal bonding, adhesive bonding, and various hybrids of those methods. In order to facilitate thin wafer processing with existing fab equipment, we developed total solutions for temporary bonding and debonding of carrier wafers. When it comes to TSV integration,...
This paper reports a hermetic MEMS package structure with silicon wafer as bonded cap at wafer-level scale. CMP followed by spraying chemical smoothing process is utilized to thin the N(100) silicon cap wafer to the thickness of 150 mum after wafer-level Cu/Sn isothermal solidification bonding. Method for the thinning process and parameters for Cu/Sn isothermal solidification bonding process are researched...
This paper presents an innovative structure based on 3 dimensional integration technology, where ultra thin inter layer dielectric enables a dynamic threshold voltage (VTH) control. A sequential process flow is proposed to fabricate 3D devices with dynamically tunable VTH. This ability can be exploited to design SRAMs cells with increased stability and surface density compared to planar technology...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.